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參數(shù)資料
| 型號： | ISPPAC-POWR1014-01TN48I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| 中文描述： | 10-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48 |
| 封裝： | LEAD FREE, TQFP-48 |
| 文件頁數(shù)： | 35/45頁 |
| 文件大小： | 999K |
| 代理商： | ISPPAC-POWR1014-01TN48I |
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Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
35
instructions are defined that access all data registers and perform other internal control operations. For compatibil-
ity between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func-
tionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by
the manufacturer. The two required registers are the bypass and boundary-scan registers. Figure 29 shows how
the instruction and various data registers are organized in an ispPAC-POWR1014/A.
Figure 29. ispPAC-POWR1014/A TAP Registers
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as
shown in Figure 30. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)
becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-
Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But
there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
ADDRESS REGISTER (109 BITS)
E
2
CMOS
N
O
N
-VOLATILE
MEMORY
UES REGISTER (32 BITS)
IDCODE REGISTER (32 BITS)
BYPASS REGISTER (1 BIT)
I
N
STRUCTIO
N
REGISTER (8 BITS)
TEST ACCESS PORT (TAP)
LOGIC
OUTPUT
LATCH
TDI
TCK
TMS
TDO
CFG ADDRESS REGISTER (12 BITS)
M
DATA REGISTER (123 BITS)
CFG DATA REGISTER (56 BITS)
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ispPAC-POWR1014-02T48I | 功能描述:監(jiān)控電路 Prec Progm Pwr Sply Seq Mon Trim, IND RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ispPAC-POWR1014-02TN48I | 功能描述:監(jiān)控電路 Prec Prog Pwr Sply Seq Mon Trim IND P-F RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISPPAC-POWR1014A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ISPPACPOWR1014A01T48I | 制造商:Lattice Semiconductor Corporation 功能描述:Volt Supervisor Sequencer/Monitor 48-Pin TQFP |
| ispPAC-POWR1014A-01T48I | 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ A DC I RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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