參數(shù)資料
型號(hào): ISPPAC-POWR1014-01TN48I
廠商: LATTICE SEMICONDUCTOR CORP
元件分類(lèi): 電源管理
英文描述: In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
中文描述: 10-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48
封裝: LEAD FREE, TQFP-48
文件頁(yè)數(shù): 27/45頁(yè)
文件大?。?/td> 999K
代理商: ISPPAC-POWR1014-01TN48I
Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
27
command (Waiting for the DO
N
E bit to be set to 1). An alternative would be to wait for a minimum specified time
(see T
CO
N
VERT
value in the specifications) and disregard checking the DO
N
E bit.
N
ote that if the I
2
C clock rate falls below 50kHz (see F
I2C
note in specifications), the only way to insure a valid ADC
conversion is to wait the minimum specified time (T
CO
N
VERT
), as the operation of the DO
N
E bit at clock rates lower
than that cannot be guaranteed. In other words, if the I
2
C clock rate is less than 50kHz, the DO
N
E bit may or may
not assert even though a valid conversion result is available.
To insure every ADC conversion result is valid, preferred operation is to clock I
2
C at more than 50kHz and verify
DO
N
E bit status or wait for the full T
CO
N
VERT
time period between subsequent ADC convert commands. If an I
2
C
request is placed before the current conversion is complete, the DO
N
E bit will be set to 1 only after the second
request is complete.
The status of the digital input lines may also be monitored and controlled through I
2
C commands. Figure 19 shows
the I
2
C interface to the I
N
[1:4] digital input lines. The input status may be monitored by reading the I
N
PUT_STATUS
register, while input values to the PLD array may be set by writing to the I
N
PUT_VALUE register. To be able to set
an input value for the PLD array, the input multiplexer associated with that bit needs to be set to the I
2
C register set-
ting in E
2
CMOS memory otherwise the PLD will receive its input from the I
N
x pin.
Figure 19. I
2
C Digital Input Interface
The digital outputs may also be monitored and controlled through the I
2
C interface, as shown in Figure 20. The sta-
tus of any given digital output may be read by reading the contents of the associated OUTPUT_STATUS[1:0] regis-
ter.
N
ote that in the case of the outputs, the status reflected by these registers reflects the logic signal used to drive
the pin, and does not sample the actual level present on the output pin. For example, if an output is set high but is
Input_Status
Input_Value
3
3
3
PLD
Array
I
2
C Interface Unit
IN[2..4]
IN1
USERJTAG
Bit
2
3
PLD Output/Input_Value Register Select
(E2 Configuration)
IN4
IN3
IN2
IN1
1
1
1
1
b7
b0
0x06 - INPUT_STATUS
(Read Only)
b6
b5
b4
b3
b2
b1
X
X
X
X
b7
b0
0x11 - INPUT_VALUE (Read/Write)
b6
b5
b4
b3
b2
b1
MUX
MUX
I4
I3
I2
X
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