參數(shù)資料
型號： ISPPAC-CLK5610V-01TN48I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 時鐘及定時
英文描述： Backlight LED; Color:Red; Digit/Alpha Height:70mm; Forward Current:250mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:70x70mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA
中文描述： 5600 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝： LEAD FREE, TQFP-48
文件頁數(shù)： 19/47頁
文件大?。?/td> 871K
代理商： ISPPAC-CLK5610V-01TN48I
Lattice Semiconductor
ispClock5600 Family Data Sheet
19
Table 4. REFSEL and FBKSEL Operation for ispClock5620
LVTTL (3.3V)
LVCMOS (1.8V, 2.5V, 3.3V)
SSTL2
SSTL3
HSTL
Differential SSTL2
Differential SSTL3
Differential HSTL
LVDS
LVPECL (differential, 3.3V)
Each input also features internal programmable termination resistors, as shown in Figure 13. Note that all refer-
ence inputs (REFA+, REFA-, REFB+, REFB-) terminate to the REFVTT pin, while all feedback inputs (FBKA+,
FBKA-, FBKB+, FBKB-) terminate to the FBKVTT pin.
Figure 13. ispClock5600 Clock Reference and Feedback Input Structure (REFA+/- Pair Shown)
The following usage guidelines are suggested for interfacing to supported logic families.
LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)
The receiver should be set to LVCMOS or LVTTL mode, and the input signal should be connected to the ‘+’ termi-
nal of the input pair (e.g. REFA+). The ‘-’ input terminal should be left
fl
oating. CMOS transmission lines are gener-
ally source terminated, so all termination resistors should be set to the OPEN state. Figure 14 shows the proper
con
fi
guration. Please note that because switching thresholds are different for LVCMOS running at 1.8V, there is a
separate con
fi
guration setting for this particular standard.
REFSEL
Selected
Input Pair
FBKSEL
Selected
Input Pair
0
REFA+/-
0
FBKA+/-
1
REFB+/-
1
FBKB+/-
R
T
R
T
REFA-
REFA+
REFVTT
To Internal
Logic
Single-ended
Receiver
ispClock5600
Differential
Receiver
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5620V-01TN48I Backlight LED; Color:Red; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No
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ISPPAC-POWR1014-01TN48I In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ispPAC-CLK5620AV-01T100C 功能描述:時鐘驅(qū)動器及分配 ISP 0 Delay Clock Ge n w/Unv Fan-Out Buf RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5620AV-01T100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
ispPAC-CLK5620AV-01T100I 功能描述:時鐘驅(qū)動器及分配 ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5620AV-01T100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5620AV-01T48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
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