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參數(shù)資料
| 型號： | ISPPAC-CLK5610V-01TN48I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Backlight LED; Color:Red; Digit/Alpha Height:70mm; Forward Current:250mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:70x70mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
| 中文描述： | 5600 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | LEAD FREE, TQFP-48 |
| 文件頁數(shù)： | 15/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPPAC-CLK5610V-01TN48I |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
15
match. The option of which mode to use is programmable and may be set using PAC-Designer software (available
from the Lattice web site at www.latticesemi.com).
In phase-lock mode the lock detector asserts the LOCK signal as soon as a lock condition is determined. In fre-
quency-lock mode, however, the PLL must be in a locked condition for a set number of phase detector cycles
before the LOCK signal will be asserted. The number of cycles required before asserting the LOCK signal in fre-
quency-lock mode can be set from 16 through 256.
When the lock condition is lost the LOCK signal will be de-asserted immediately in both phase-lock and frequency-
lock detection modes. In frequency-lock mode, however, if the input reference signal is stopped, the LOCK output
may continue to be asserted. In phase-lock mode, a loss of the input reference signal will always result in de-asser-
tion of the LOCK output.
Loop Filter
A simpli
fi
ed schematic for the ispClock5600 loop
fi
lter is shown in Figure 11. The
fi
lter’s capacitors are
fi
xed, and
the response is controlled by setting the value of the phase-detector’s output current source’s and the value of the
variable resistor. The phase detector output current has 14 possible settings, ranging from 3μA to 55μA, while the
resistor may be set to any one of six values ranging from 2.3K to 9.3K. This provides a total of 84 unique I-R com-
binations which may be selected.
Figure 11. ispClock5600 Loop Filter (Simplified)
Because the selection of an optimal PLL loop
fi
lter can be a daunting task, PAC-Designer offers a set of default
fi
l-
ter settings which will provide acceptable performance for most applications. The primary criterion for selecting one
of these settings is the total division factor used in the feedback path, or the ratio between the VCO output fre-
quency and the frequency output by the N feedback divider (N x V
feedback
). Table 2 lists these default settings and
conditions under which they should be used.
To VCO
R
C
2
C
1
I
I
Phase Detector
From
M-divider
From
N-divider
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ispPAC-CLK5620AV-01T100C | 功能描述:時鐘驅動器及分配 ISP 0 Delay Clock Ge n w/Unv Fan-Out Buf RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5620AV-01T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ispPAC-CLK5620AV-01T100I | 功能描述:時鐘驅動器及分配 ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5620AV-01T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5620AV-01T48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
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