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參數(shù)資料
| 型號： | ISPLSI2192VE-100LB144 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 3/15頁 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 96I/O 10NS 144FPBGA |
| 標準包裝： | 160 |
| 系列： | ispLSI® 2000VE |
| 可編程類型： | 系統(tǒng)內可編程 |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 48 |
| 宏單元數(shù)： | 192 |
| 門數(shù)： | 8000 |
| 輸入/輸出數(shù)： | 96 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-BGA |
| 供應商設備封裝： | 144-FPBGA（13x13） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI 2192VE-100LB144 ISPLSI 2192VE-100LB144-ND Q6436683 |
Specifications ispLSI 2192VE
11
RESET
15
G4
GOE 0, GOE 1
80, 17
F12, G2
Y0, Y1, Y2
14, 83, 78
F3, F10, G11
BSCAN
19
F1
TDI/IN 0
20
G3
TMS/IN 1
48
J6
TDO/IN 6
112
C7
TCK/IN 7
77
G12
IN 2-5, IN 8-11
—, 49, 82, —, 84, 113, 13, —
M7, J7, F9, G10, E12, B6,
F2, E1
GND
18, 34, 50, 63, 79, 98, 111,
A1, A12, D4, D9, E5, E8, F6,
127
F7, G6, G7, H5, H8, J4, J9,
M1, M12
VCC
2, 16, 31, 47, 66, 81, 95, 114
B1, B12, E6, E7, F5, F8, G5,
G8, H6, H7, L1, L12
NC1
—K2
Signal Descriptions
RESET
Active Low (0) Reset pin resets all the registers in the device.
GOE 0, GOE1
Global Output Enable input pins.
Y0, Y1, Y2
Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in
the device.
BSCAN
Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0
Input – This pin performs two functions. When
BSCAN is logic low, it functions as a serial data input pin
to load programming data into the device. When
BSCAN is high, it functions as a dedicated input pin.
TCK/IN 7
Input – This pin performs two functions. When
BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. When
BSCAN is high, it functions as a dedicated input pin.
TMS/IN 1
Input – This pin performs two functions. When
BSCAN is logic low, it functions as a mode control pin for
the Boundary Scan state machine. When
BSCAN is high, it functions as a dedicated input pin.
TDO/IN 6
Output/Input – This pin performs two functions. When
BSCAN is logic low, it functions as an output pin
to read serial shift register data. When
BSCAN is high, it functions as a dedicated input pin.
IN 2-5, IN 8-11
Dedicated Input Pins to the device.
GND
Ground (GND)
VCC
Vcc
NC1
No Connect
I/O
Input/Output Pins – These are the general purpose I/O pins used by the logic array.
Signal Name
Description
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Locations
Signal Name
128-Pin TQFP
144-Ball fpBGA
1. NC pins are not to be connected to any active signals, VCC or GND.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2192VE-100-LB144 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2192VE100LB144I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2192VE-100LT | 制造商:Lattice Semiconductor Corporation 功能描述:2192VE-100LT |
| ISPLSI2192VE100LT128 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD |
| ISPLSI2192VE-100LT128 | 功能描述:CPLD - 復雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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