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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ISPLSI2192VE-100LB144 |
| 寤犲晢锛� | Lattice Semiconductor Corporation |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 14/15闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PLD ISP 96I/O 10NS 144FPBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 160 |
| 绯诲垪锛� | ispLSI® 2000VE |
| 鍙法绋嬮(l猫i)鍨嬶細 | 绯荤当(t菕ng)鍏�(n猫i)鍙法绋� |
| 鏈€澶у欢閬叉檪(sh铆)闁� tpd(1)锛� | 10.0ns |
| 闆诲闆绘簮 - 鍏�(n猫i)閮細 | 3 V ~ 3.6 V |
| 閭忚集鍏冧欢/閭忚集濉婃暩(sh霉)鐩細 | 48 |
| 瀹忓柈鍏冩暩(sh霉)锛� | 192 |
| 闁€(m茅n)鏁�(sh霉)锛� | 8000 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 96 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤�(l猫i)鍨嬶細 | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 144-BGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 144-FPBGA锛�13x13锛� |
| 鍖呰锛� | 鎵樼洡(p谩n) |
| 鍏跺畠鍚嶇ū(ch膿ng)锛� | ISPLSI 2192VE-100LB144 ISPLSI 2192VE-100LB144-ND Q6436683 |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)鐣�(d膩ng)鍓嶇14闋�(y猫)绗�15闋�(y猫)
Specifications ispLSI 2192VE
8
Internal Timing Parameters1
Over Recommended Operating Conditions
tio
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036D/2192VE v0.1
Inputs
UNITS
-135
MIN.
-100
MIN.
MAX.
DESCRIPTION
#
2
PARAMETER
20 Input Buffer Delay
鈥�
ns
tdin
21 Dedicated Input Delay
鈥�
ns
tgrp
22 GRP Delay
鈥搉s
GLB
t1ptxor
25 1 Product Term/XOR Path Delay
鈥�
ns
t20ptxor
26 20 Product Term/XOR Path Delay
鈥�
ns
txoradj
27 XOR Adjacent Path Delay
鈥�
ns
tgbp
28 GLB Register Bypass Delay
鈥�
ns
tgsu
29 GLB Register Setup Time before Clock
1.7
ns
tgh
30 GLB Register Hold Time after Clock
4.8
ns
tgco
31 GLB Register Clock to Output Delay
鈥�
ns
3
tgro
32 GLB Register Reset to Output Delay
鈥�
ns
tptre
33 GLB Product Term Reset to Register Delay
鈥�
ns
tptoe
34 GLB Product Term Output Enable to I/O Cell Delay
鈥�
ns
tptck
35 GLB Product Term Clock Delay
2.6
ns
ORP
tob
38 Output Buffer Delay
鈥�
ns
tsl
39 Output Slew Limited Delay Adder
鈥�
ns
GRP
t4ptbpc
23 4 Product Term Bypass Path Delay (Combinatorial)
鈥�
ns
t4ptbpr
24 4 Product Term Bypass Path Delay (Registered)
鈥�
ns
torp
36 ORP Delay
鈥搉s
torpbp
37 ORP Bypass Delay
鈥�
ns
Outputs
toen
40 I/O Cell OE to Output Enabled
鈥�
ns
todis
41 I/O Cell OE to Output Disabled
鈥�
ns
tgoe
42 Global Output Enable
鈥�
ns
tgy0
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
2.4
ns
tgy1/2
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.6
ns
Clocks
tgr
45 Global Reset to GLB
鈥�
0.7
2.5
1.8
6.2
1.0
鈥�
0.3
3.1
7.1
9.1
5.6
1.6
2.0
5.2
4.7
1.7
0.7
3.4
5.6
2.4
2.6
7.1
0.5
1.7
1.2
4.7
0.5
鈥�
0.3
1.1
6.1
6.9
4.6
1.6
2.0
3.7
1.5
0.5
3.4
3.6
1.6
1.8
5.8
鈥�
1.2
3.8
鈥�
1.6
鈥�
1.6
1.8
鈥搉s
Global Reset
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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|---|---|
| ISPLSI2192VE-100-LB144 | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū(ch膿ng):Lattice Semiconductor 鍔熻兘鎻忚堪:3.3V In-System Programmable SuperFAST鈶� High Density PLD |
| ISPLSI2192VE100LB144I | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū(ch膿ng):Lattice Semiconductor 鍔熻兘鎻忚堪:3.3V In-System Programmable SuperFAST鈶� High Density PLD |
| ISPLSI2192VE-100LT | 鍒堕€犲晢:Lattice Semiconductor Corporation 鍔熻兘鎻忚堪:2192VE-100LT |
| ISPLSI2192VE100LT128 | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū(ch膿ng):Lattice Semiconductor 鍔熻兘鎻忚堪:3.3V In-System Programmable SuperFAST鈶� High Density PLD |
| ISPLSI2192VE-100LT128 | 鍔熻兘鎻忚堪:CPLD - 寰�(f霉)闆滃彲绶ㄧ▼閭忚集鍣ㄤ欢 RoHS:鍚� 鍒堕€犲晢:Lattice 绯诲垪: 瀛樺劜(ch菙)椤�(l猫i)鍨�:EEPROM 澶ч浕姹�?c谩i)?sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:333 MHz 寤堕伈鏅�(sh铆)闁�:2.7 ns 鍙法绋嬭几鍏�/杓稿嚭绔暩(sh霉)閲�:64 宸ヤ綔闆绘簮闆诲:3.3 V 鏈€澶у伐浣滄韩搴�:+ 90 C 鏈€灏忓伐浣滄韩搴�:0 C 灏佽 / 绠遍珨:TQFP-100 |
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