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參數(shù)資料
| 型號(hào)： | ISPLSI 1024-90LJ |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 48I/O 12NS 68PLCC |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | ispLSI® 1000 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 12.0ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數(shù)目： | 24 |
| 門數(shù)： | 4000 |
| 輸入/輸出數(shù)： | 48 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
| 包裝： | 管件 |
| 其它名稱： | ISPLSI1024-90LJ |
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Specifications ispLSI 1024
10
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
NAME
Table 2 - 0002C-24
PLCC and JLCC
PIN NUMBERS
DESCRIPTION
22,
26,
30,
37,
41,
45,
56,
60,
64,
3,
7,
11,
23,
27,
31,
38,
42,
46,
57,
61,
65,
4,
8,
12,
24,
28,
32,
39,
43,
47,
58,
62,
66,
5,
9,
13,
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
25,
29,
33,
40,
44,
48,
59,
63,
67,
6,
10,
14
54
Y1
16
Y0
55
MODE/IN 31
Input - This pin performs two functions. When ispEN is logic low, it
functions as pin to control the operation of the isp state machine. It is a
dedicated input pin when ispEN is logic high.
Ground (GND)
GND
V
VCC
CC
IN 4 - IN 5
2,
15
Input - These pins are dedicated input pins to the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO
and SCLK options become active.
19
ispEN
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 is also used as one of the two control pins for the isp state
machine. It is a dedicated input pin when ispEN is logic high.
21
SDI/IN 01
34
SDO/IN 11
Output/Input - This pin performs two functions. When ispEN is logic low,
it functions as an output pin to read serial shift register data. It is a
dedicated input pin when ispEN is logic high.
49
SCLK/IN 21
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated
input pin when ispEN is logic high.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
20
RESET
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
51
Y2
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
50
Y3
1,
18,
35,
52
17,
36,
53,
68
19,
23,
31,
42,
46,
54,
69,
73,
81,
92,
96,
4,
20,
28,
32,
43,
47,
55,
70,
78,
82,
93,
97,
5,
21,
29,
33,
44,
48,
56,
71,
79,
83,
94,
98,
6,
22,
30,
34,
45,
53,
57,
72,
80,
84,
95,
3,
7
67
9
68
91,
8
16
18
35
58
17
60
59
14,
15,
36,
37,
10,
11,
40,
41,
61,
62,
89,
90
65,
66,
85,
86
TQFP PIN NUMBERS
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, Vcc or GND.
No Connect
NC2
—
1,
2,
12,
13,
24,
25,
26,
27,
38,
39,
49,
50,
51,
52,
63
64,
74,
75,
76,
77
87,
88,
99, 100
Pin Description
ALL
DEVICES
DISCONTINUED
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI 1024EA-200LT100 | IC PLD ISP 48I/O 10NS 100TQFP |
| ISPLSI 1032-90LT | IC PLD ISP 64I/O 12NS 100TQFP |
| ISPLSI 1032E-125LJN | IC PLD ISP 64I/O 7.5NS 84PLCC |
| ISPLSI 1032EA-200LT100 | IC PLD ISP 64I/O 4.5NS 100TQFP |
| ISPLSI 1048-50LQI | IC PLD ISP 96I/O 18NS 120PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI1024-90LJ | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI102490LT | 制造商:LATT 功能描述: |
| ISPLSI1024-90LT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI1024EA-100LT100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI1024EA-125LT100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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