- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1929 > ISPLSI 1032EA-200LT100 (Lattice Semiconductor Corporation)IC PLD ISP 64I/O 4.5NS 100TQFP PDF資料下載
參數(shù)資料
| 型號： | ISPLSI 1032EA-200LT100 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 64I/O 4.5NS 100TQFP |
| 標準包裝： | 90 |
| 系列： | ispLSI® 1000EA |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 4.5ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數(shù)目： | 32 |
| 門數(shù)： | 6000 |
| 輸入/輸出數(shù)： | 64 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI1032EA-200LT100 |
ispLSI 1032EA
In-System Programmable High Density PLD
1032ea_04
1
USE
ispMA
CH
4A5
FOR
NEW
5V
DESIGNS
Functional Block Diagram
Features
HIGH DENSITY PROGRAMMABLE LOGIC
— 6000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 192 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— Functionally Compatible with ispLSI 1032E
NEW FEATURES
— 100% IEEE 1149.1 Boundary Scan Testable
— ispJTAG In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User Selectable 3.3V or 5V I/O Supports Mixed-
Voltage Systems (VCCIO Pin)
— Open-Drain Output Option
HIGH PERFORMANCE E2CMOS TECHNOLOGY
—
fmax = 200 MHz Maximum Operating Frequency
—
tpd = 4.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
Output
Routing
Pool
Output
Routing
Pool
CLK
Global Routing Pool (GRP)
0139A/1032EA
Logic
Array
DQ
GLB
Description
The ispLSI 1032EA is a High Density Programmable
Logic Device containing 192 Registers, 64 Universal I/O
pins, four Dedicated Input pins, four Dedicated Clock
Input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 1032EA features 5V in-system
programmability (ISP) and in-system diagnostic capa-
bilities via IEEE 1149.1 Test Access Port. The ispLSI
1032EA device offers non-volatile reprogrammability of
the logic, as well as the interconnects to provide truly
reconfigurable systems. A functional superset of the
ispLSI 1032 architecture, the ispLSI 1032EA device adds
user selectable 3.3V or 5V I/O and open-drain output
options.
The basic unit of logic on the ispLSI 1032EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…D7 (Figure 1). There are a total of 32 GLBs in the
ispLSI 1032EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinato-
rial or registered. Inputs to the GLB come from the GRP
and dedicated inputs. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
January 2002
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI 1048-50LQI | IC PLD ISP 96I/O 18NS 120PQFP |
| ISPLSI 1048C-50LQI | IC PLD ISP 96I/O 22NS 128PQFP |
| ISPLSI 1048E-125LTN | IC PLD ISP 96I/O 7.5NS 128TQFP |
| ISPLSI 1048EA-170LT128 | IC PLD ISP 96I/O 5NS 128TQFP |
| ISPLSI 2032A-180LJN44 | IC PLD ISP 32I/O 5NS 44PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI1032EA-200LT100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI103L-80LJ | 制造商:LATT 功能描述: |
| ISPLSI1048-50LG/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ispLSI1048-50LQ | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ispLSI1048-50LQI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。