參數(shù)資料
型號: ISPGDXTMFAMILY
廠商: Lattice Semiconductor Corporation
元件分類: TVS-瞬態(tài)抑制二極管
英文描述: JT 100C 100#22D PIN RECP
中文描述: 在系統(tǒng)可編程通用數(shù)字CrosspointTM
文件頁數(shù): 15/25頁
文件大?。?/td> 326K
代理商: ISPGDXTMFAMILY
15
Specifications
ispGDX Family
The ispGDX devices are identified either by the 32-bit
JTAG IDCODE register or the eight-bit ISP register. The
device ID assignments are listed in Table 4.
The ispJTAG programming is accomplished by execut-
ing Lattice private instructions under the Boundary Scan
State Machine.
Lattice ISP programming is accomplished by driving
BSCAN/
ispEN
low, while following the ISP state machine
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
1
0
1
0
1
1
1
0
1
0
0
1
1
1
0
0
1
Update-IR
Exit2-IR
Pause-IR
Exit1-IR
Shift-IR
Capture-IR
Select-IR-Scan
Update-DR
Exit2-DR
Pause-DR
Exit1-DR
Shift-DR
Capture-DR
Select-DR-Scan
Run-Test/Idle
Test-Logic-Reset
TCK
TMS or
TDI
TDO
t
su
t
h
t
co
tsu = 0.1
μ
s (min.) th = 0.1
μ
s (min.) tco = 0.1
μ
s (min.)
Figure 8. Boundary Scan State Machine
Boundary Scan / ISP Programming and Test Options (Continued)
algorithm. The eight-bit device ID can be read from the
device in Idle State for ISP device identification. Details
of the programming sequence are transparent to the user
and are handled by Lattice ISP Daisy Chain Downlowad
(ispDCD), ispCODE
C
routines or any third-party pro-
grammers. Contact Lattice Technical Support to obtain
more detailed programming information.
Table 4. ispGDX Device ID Codes
GDX ID Codes
0000 0000 0010 0101 0001 0000 0100 0011
0000 0000 0010 0101 0011 0000 0100 0011
ispGDX80A
ispGDX160/A
0111 0111
0000 0000 0010 0101 0010 0000 0100 0011
ispGDX120A
0111 1000
0111 1001
8-BIT ISP ID
32-BIT BOUNDARY SCAN IDCODE
DEVICE
相關PDF資料
PDF描述
ISPGDX160A-5B272 In-System Programmable Generic Digital CrosspointTM
ISPGDX80VA-7T100 In-System Programmable 3.3V Generic Digital CrosspointTM
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ISPGDX80VA-5T100 In-System Programmable 3.3V Generic Digital CrosspointTM
ISPGDX80VA-5T100I In-System Programmable 3.3V Generic Digital CrosspointTM
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