參數(shù)資料
型號(hào): ISP1161ABM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 61/134頁
文件大?。?/td> 587K
代理商: ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
61 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.3.4
HcRhPortStatus[1:2] register (R/W [1]:15H/95H, [2]: 16H/96H)
The HcRhPortStatus[1:2] register is used to control and report port events on a
per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus
registers that are implemented in hardware. The lower word is used to reflect the port
status, whereas the upper word reflects the status change bits. Some status bits are
implemented with special write behavior. If a transaction (token through handshake)
is in progress when a write to change port status occurs, the resulting port status
change must be postponed until the transaction completes. Reserved bits should
always be written logic 0.
Code (Hex): [1] = 15, [2] = 16 —
read
Code (Hex): [1] = 95, [2] = 96 —
write
Table 34:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcRhPortStatus[1:2] register: bit allocation
31
30
29
28
27
26
25
24
reserved
0
0
0
0
0
0
0
0
R/W
23
R/W
22
R/W
21
R/W
20
PRSC
0
R/W
12
R/W
19
OCIC
0
R/W
11
R/W
18
PSSC
0
R/W
10
R/W
17
PESC
0
R/W
9
LSDA
0
R/W
1
PES
0
R/W
R/W
16
CSC
0
R/W
8
PPS
0
R/W
0
CCS
0
R/W
reserved
0
R/W
14
0
0
R/W
15
R/W
13
reserved
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
4
PRS
0
R/W
R/W
3
POCI
0
R/W
R/W
2
PSS
0
R/W
reserved
0
R/W
0
0
R/W
R/W
Table 35:
Bit
31 to 21
20
HcRhPortStatus[1:2] register: bit description
Symbol
Description
-
reserved
PRSC
PortResetStatusChange:
This bit is set at the end of the 10 ms
port reset signal. The HCD writes logic 1 to clear this bit. Writing
logic 0 has no effect.
0 —
port reset is not complete
1 —
port reset is complete
PortOverCurrentIndicatorChange:
This bit is valid only if
overcurrent conditions are reported on a per-port basis. This bit is
set when Root Hub changes the PortOverCurrentIndicator bit. The
HCD writes logic 1 to clear this bit. Writing logic 0 has no effect.
19
OCIC
0 —
no change in PortOverCurrentIndicator
1 —
PortOverCurrentIndicator has changed
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