參數(shù)資料
型號: ISP1161ABM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 18/134頁
文件大?。?/td> 587K
代理商: ISP1161ABM
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
18 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
In
Figure 17
and
Figure 18
, the hardware is configured such that DREQ is active
HIGH and DACK is active LOW.
8.6 Interrupts
The ISP1161A has separate interrupt request pins for the USB HC (INT1) and the
USB DC (INT2).
8.6.1
Pin configuration
The interrupt output signals have four configuration modes:
Mode 0
Mode 1
Mode 2
Mode 3
Level trigger, active LOW (default at power-up)
Level trigger, active HIGH
Edge trigger, active LOW
Edge trigger, active HIGH.
Figure 19
shows these four interrupt configuration modes. They are programmable
via the HcHardwareConfiguration register (see
Section 10.4.1
), which are also used
to disable or enable the signals.
N = 1/2 byte count of transfer data, K = number of cycles/burst.
Fig 18. DMA transfer in burst mode.
004aaa104
data #1
data #K
data #2K
data #N
data #(K
+
1)
data #(N
K
+
1)
DREQ
DACK
D[15:0]
EOT
RD or WR
相關(guān)PDF資料
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ISP1161 Full-speed Universal Serial Bus single-chip host and device controller
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