31 FN7973.2 April 25, 2013 ADDRESS 0XC1: USER_PATT1_LSB ADDRESS 0XC2: USER_PATT1_MSB These registers define the lower and upper eigh" />
參數(shù)資料
型號： ISLA214S50IR1Z
廠商： Intersil
文件頁數(shù)： 25/41頁
文件大?。?/td> 0K
描述： IC ADC
標(biāo)準(zhǔn)包裝： 1
系列： *
ISLA214S50
31
FN7973.2
April 25, 2013
ADDRESS 0XC1: USER_PATT1_LSB
ADDRESS 0XC2: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 1.
ADDRESS 0XC3: USER_PATT2_LSB
ADDRESS 0XC4: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 2.
ADDRESS 0XC5: USER_PATT3_LSB
ADDRESS 0XC6: USER_PATT3_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 3.
ADDRESS 0XC7: USER_PATT4_LSB
ADDRESS 0XC8: USER_PATT4_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 4.
ADDRESS 0XC9: USER_PATT5_LSB
ADDRESS 0XCA: USER_PATT5_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 5.
ADDRESS 0XCB: USER_PATT6_LSB
ADDRESS 0XCC: USER_PATT6_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 6.
ADDRESS 0XCD: USER_PATT7_LSB
ADDRESS 0XCE: USER_PATT7_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XD0: USER_PATT8_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
ADDRESS 0xDF - 0xF3: JESD204 REGISTERS
Address 0xDF-0xEE: JESD204 Parameter
Interface
This set of registers controls the JESD204 transmitter
configuration. By programming these parameters, the system
can select between efficient and simple packing, select the
number of powered up SERDES lanes, choose the ADC resolution
transmitted, and so on. Contact the factory for details.
0xE0 through 0xED are the JESD204 parameter registers. These
parameters are written to set the transport layer mapping of the
JESD204 transmitter in this product family. These registers can
be written to shift between efficient and simple packing, to
enable or bypass scrambling, and to reduce the number of
powered up lanes used in the link. Each speed graded product
allows downgrading of the JESD204 link (such as reducing the
number of lanes, reducing the converter resolution, etc), but not
upgrading. These parameters are communicated on every lane
of the link during the 2nd multi-frame of the initial lane
alignment sequence, and therefore can be used by a generic
JESD204A or JESD204B receiver that supports the given
configuration. See the JESD204A or JESD204B specification for
additional information on how these registers are used in a
JESD204 system, including encoding rules.
ADDRESS 0XDF: JESD204_UPDATE_CONFIG_START
Bit 0 update_start
This self-resetting bit is used to indicate that some or all the
JESD204 parameters (addresses 0xE0 through 0xED) are going
to be written. Writing a '1' to this bit will hold the JESD204 PLL
and transmitter in a reset state while these parameters are
written, because these parameters can affect the transmitter's
dynamic behavior (such as modifying the PLL's frequency
multiplication). The bit will automatically reset to a '0' once a '1'
is written to address 0xEE Bit[0] "update_complete". The
recommended sequence for modifying the JESD204 transmitter
is:
1. Write a '1' to 0xDF Bit[0]
2. Write some or all modified values to 0xE0 through 0xEC
3. Write a '1' to 0xEE Bit[0]. Note: 0xDF Bit[0] and 0xEE Bit[0] will
automatically be reset to a '0' once configuration has been
applied to the circuitry.
ADDRESS 0XE0: JESD204_CONFIG_0
Bits 7:0 “DID”, JESD204 Device Identification Number.
ADDRESS 0XE1: JESD204_CONFIG_1
Bits 3:0 “BID”, JESD204 Bank ID.
ADDRESS 0XE2: JESD204_CONFIG_2
Bits 4:0 “LID” JESD204 Lane Identification Number.
ADDRESS 0XE3: JESD204_CONFIG_3
Bit 7 "SCR", JESD204 SCR controls if scrambling across the
SERDES lane(s) is enabled ('1' means enabled).
Bits 4:0 "L", JESD204 number of SERDES lanes in the link.
ADDRESS 0XE4: JESD204_CONFIG_4
Bits 7:0 “F”, JESD204 number of octets per frame.
ADDRESS 0XE5: JESD204_CONFIG_5
Bits 4:0 "K", JESD204 Number of frame periods per multi-frame
period. This product family supports the full programmable
range of K (decimal 0 through 31), although note that the
JESD204 standard dictates a minimum number for this
parameter that is configuration dependent. There must be at
least 17 and no more than 1024 octets per multiframe. K must
be set to meet this constraint.
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