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參數(shù)資料
| 型號(hào)： | ISLA214S50IR1Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/41頁 |
| 文件大小： | 0K |
| 描述： | IC ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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ISLA214S50
19
FN7973.2
April 25, 2013
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation significantly while taking a very short time to return to
functionality. Sleep mode reduces power consumption drastically
while taking longer to return to functionality.
In Nap mode the JESD204 lanes will continue to produce valid
encoded data, allowing the link to remain active and thus return to
a functional state quickly. The data transmitted over the lanes in
nap mode is the last valid ADC sample, repeated until leaving nap
mode. The 8b/10b encoder’s running disparity will prevent the
potentially long time repetition of this last valid sample from
creating DC bias on the lane. In sleep mode the JESD204 lanes will
be deactivated to conserve power. Thus, sometime after wake up
code group alignment will be required to reestablish the link.
The input clock should remain running and at a fixed frequency
during Nap or Sleep, and CSB should be high. The JESD204 link
will only remain established during nap mode if the input clock
continues to remain stable during the nap period.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2. Please note
that power on calibration occurs at power up time regardless of
the state of the NAPSLP pin; immediately following this power on
calibration routine the device will enter nap or sleep state if the
NAPSLP pin voltage dictates it is to do so.
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. However, if the ADC
is powered-on with the NAPSLP pin in either Nap or Sleep modes,
the pin must be first set to Normal before the SPI port will be
enabled. Therefore, before the SPI port can be used to override
the NAPSLP pin setting, the ADC must have been put into Normal
mode at least once using the NAPSLP pin. Further details on the
SPI port are contained in “Serial Peripheral Interface” on
Data Format
Output data can be presented in three formats: two’s
complement(default), Gray code and offset binary. The data
format can be controlled through the SPI port by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 39 shows this
operation.
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 40.
Mapping of the input voltage to the various data formats is
shown in Table 3.
.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Nap
AVDD
Sleep
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full Scale 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000
–Full Scale
+ 1LSB
00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001
Mid–Scale 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000
+Full Scale
– 1LSB
11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001
+Full Scale 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000
FIGURE 39. BINARY TO GRAY CODE CONVERSION
12
13
11
0
1
BINARY
12
13
11
0
GRAY CODE
1
FIGURE 40. GRAY CODE TO BINARY CONVERSION
12
13
11
0
1
BINARY
12
13
11
0
GRAY CODE
1
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