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參數(shù)資料
| 型號： | ISLA212P20IRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL/SPI 72QFN |
| 標準包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 468mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | * |
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ISLA212P
21
FN7717.2
November 30, 2012
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 25. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52μs to regain lock at 250MSPS. The lock time is
inversely proportional to the sample rate.
The DLL has two ranges of operation: slow and fast. The slow
range can be used for sample rates between 40MSPS and
100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
illustrated in Figure 32.
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure1A. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion
(not statistically correlated), which determines the total jitter in
the system. The total jitter, combined with other noise sources,
then determines the achievable SNR.
Voltage Reference
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional to the
reference voltage. The nominal value of the voltage reference is
1.25V.
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible
(default) or CMOS modes. In either case, the data is presented in
relationships for LVDS and CMOS modes, respectively.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA (default) or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the A/D. The applicability of this setting is
dependent upon the PCB layout; therefore, the user should
experiment to determine whether performance degradation is
observed.
The output mode can be controlled through the SPI port by
writing to address 0x73 (see “Serial Peripheral Interface” on
An external resistor creates the bias for the LVDS drivers. A 10k
Ω,
1% resistor must be connected from the RLVDS pin to OVSS.
Power Dissipation
The power dissipated by the ISLA212P is primarily dependent on
the sample rate and the output modes: LVDS vs CMOS and DDR
vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode but is more strongly related to the clock frequency in
CMOS mode.
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to < 60mW while Sleep mode reduces power
dissipation to 9mW typically.
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52s
to regain lock at 250MSPS.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 25.
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
SNR
20 log10
1
2
πfINtJ
-------------------
=
(EQ. 1)
FIGURE 32. SNR vs CLOCK JITTER
tj = 100ps
tj = 10ps
tj = 1ps
tj = 0.1ps
10 BITS
12 BITS
14 BITS
50
55
60
65
70
75
80
85
90
95
100
1M
10M
100M
1G
S
N
R
(dB)
INPUT FREQUENCY (Hz)
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
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