18 FN7717.2 November 30, 2012 User Initiated Reset Recalibration of the A/D can be initiated at any time by driving the RESETN pin low" />
參數(shù)資料
型號(hào)： ISLA212P20IRZ
廠商： Intersil
文件頁(yè)數(shù)： 10/36頁(yè)
文件大小： 0K
描述： IC ADC 12BIT SRL/SPI 72QFN
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 12
采樣率（每秒）： 200M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 468mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： *
ISLA212P
18
FN7717.2
November 30, 2012
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength in its high impedance
state of less than 0.5mA is recommended, as RESETN has an
internal high impedance pull-up to OVDD. As is the case during
power-on reset, RESETN and DNC pins must be in the proper
state for the calibration to execute successfully.
The performance of the ISLA212P changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance is achieved by
recalibrating the A/D under the environmental conditions at
which it will operate.
A supply voltage variation of <100mV generally results in an SNR
change of <0.5dBFS and an SFDR change of <3dBc.
In situations where the sample rate is not constant, best results
are obtained if the device is calibrated at the highest sample
rate. Reducing the sample rate by less than 80MSPS typically
results in an SNR change of <0.5dBFS and an SFDR change of
<3dBc.
Figures 21 through 26 show the effect of temperature on SNR
and SFDR performance, with power-on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power-on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated previously. However, it can be
seen that performance drift with temperature is not a very strong
function of the temperature at which the power-on calibration is
performed.
FIGURE 19. A/D CORE BLOCK DIAGRAM
DIGITAL
ERROR
CORRECTION
SHA
1.25V
INP
INN
CLOCK
GENERATION
2.5- BIT
FLASH
6- STAGE
1.5- BIT/ STAGE
3- STAGE
1-BIT/ STAGE
3- BIT
FLASH
+
–
FLASH
2.5-BIT
LVDS/LVCMOS
OUTPUTS
FIGURE 20. CALIBRATION TIMING
CLKP
CLKN
CLKOUTP
CALIBRATION
BEGINS
CALIBRATION
COMPLETE
CALIBRATION
TIME
RESETN
CAL_STATUS
BIT
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