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參數(shù)資料
| 型號： | ISL98001CQZ-210 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Triple Video Digitizer with Digital PLL |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | 14 x 20 MM, ROHS COMPLIANT, PLASTIC, MS-022, MQFP-128 |
| 文件頁數(shù)： | 24/29頁 |
| 文件大?。?/td> | 470K |
| 代理商： | ISL98001CQZ-210 |
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24
FN6148.0
October 25, 2005
If there is a SOG signal, the TriLevel Detect bit will operate
correctly for standard trilevel sync levels (600mV
P-P
). In
some real-world situations, the peak-to-peak sync amplitude
may be significantly smaller, sometimes 300mV
P-P
or less.
In these cases the sync slicer will continue to operate
correctly, but the TriLevel Detect bit may not be set. Trilevel
detection accuracy can be enhanced by polling the trilevel
bit multiple times. If HSYNC is inactive, SOG is present, and
the TriLevel Sync Detect bit is read as a 1, there is a high
likelihood there is trilevel sync.
CSYNC Present
If a composite sync source (either CSYNC on HSYNC or
SOG) is selected through bits 3 and 4 of register 0x05, the
CSYNC Present bit in register 0x01 should be set. CSYNC
Present detects the presence of a low frequency, repetitive
signal inside HSYNC, which indicates a VSYNC signal. The
CSYNC Present bit should be used to confirm that the signal
being received is a reliable composite sync source.
SYNC Output Signals
The ISL98001 has 2 pairs of HSYNC and VSYNC output
signals, HSYNC
OUT
and VSYNC
OUT
, and HS
OUT
and
VS
OUT
.
HSYNC
OUT
and VSYNC
OUT
are buffered versions of the
incoming sync signals; no synchronization is done. These
signals are used for mode detection
HS
OUT
and VS
OUT
are generated by the ISL98001’s logic
and are synchronized to the output DATACLK and the digital
pixel data on the output databus. HS
OUT
is used to signal
the start of a new line of digital data. VS
OUT
is not needed in
most applications.
Both HSYNC
OUT
and VSYNC
OUT
(including the sync
separator function) remain active in power-down mode. This
allows them to be used in conjunction with the Sync Status
registers to detect valid video without powering up the
ISL98001.
HSYNC
OUT
HSYNC
OUT
is an unmodified, buffered version of the incoming
HSYNC
IN
or SOG
IN
signal of the selected channel, with the
incoming signal’s period, polarity, and width to aid in mode
detection. HSYNC
OUT
will be the same format as the incoming
sync signal: either horizontal or composite sync. If a SOG input
is selected, HSYNC
OUT
will output the entire SOG signal,
including the VSYNC portion, pre-/post-equalization pulses if
present, and Macrovision pulses if present. HSYNC
OUT
remains active when the ISL98001 is in power-down mode.
HSYNC
OUT
is generally used for mode detection.
VSYNC
OUT
VSYNC
OUT
is an unmodified, buffered version of the
incoming VSYNC
IN
signal of the selected channel, with the
original VSYNC period, polarity, and width to aid in mode
detection. If a SOG input is selected, this signal will output
the VSYNC signal extracted by the ISL98001’s sync slicer.
Extracted VSYNC will be the width of the embedded VSYNC
pulse plus pre- and post-equalization pulses (if present).
Macrovision pulses from an NTSC DVD source will lengthen
the width of the VSYNC pulse. Macrovision pulses from
other sources (PAL DVD or videotape) may appear as a
second VSYNC pulse encompassing the width of the
Macrovision. See the Macrovision section for more
information. VSYNC
OUT
(including the sync separator
function) remains active in power-down mode. VSYNC
OUT
is generally used for mode detection, start of field detection,
and even/odd field detection.
HS
OUT
HS
OUT
is generated by the ISL98001’s control logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its trailing edge is aligned with
pixel 0. Its width, in units of pixels, is determined by register
0x19, and its polarity is determined by register 0x18[7]. As
the width is increased, the trailing edge stays aligned with
pixel 0, while the leading edge is moved backwards in time
relative to pixel 0. HS
OUT
is used by the scaler to signal the
start of a new line of pixels.
The HS
OUT
Width register (0x19) controls the width of the
HS
OUT
pulse. The pulse width is nominally 1 pixel clock
period times the value in this register. In the 48 bit output
mode (register 0x18[0] = 1), or the YPbPr input mode
(register 0x05[2] = 1), the HS
OUT
width is incremented in 2
pixel clock (1 DATACLK) increments (See Table 6).
TABLE 5. SYNC SOURCE DETECTION TABLE
HSYNC
DETECT
VSYNC
DETECT
SOG
DETECT
TRILEVEL
DETECT
RESULT
1
1
X
X
Sync is on HSYNC and VSYNC
1
0
X
X
Sync is composite sync on HSYNC. Set Input configuration register to CSYNC on
HSYNC and confirm that CSYNC detect bit is set.
0
0
1
0
Sync is composite sync on SOG. It is possible that trilevel sync is present but amplitude
is too low to set trilevel detect bit. Use video mode table to determine if this video mode
is likely to have trilevel sync, and set clamp start, width values appropriately if it is.
0
0
1
1
Sync is composite sync on SOG. Sync is likely to be trilevel.
0
0
0
X
No valid sync sources on any input.
ISL98001
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| ISL98001CQZ-240 | 功能描述:IC TRPL VIDEO DIGITIZER 128-MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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