參數(shù)資料
型號(hào)： ISL98001CQZ-210
廠商： INTERSIL CORP
元件分類： 消費(fèi)家電
英文描述： Triple Video Digitizer with Digital PLL
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： 14 x 20 MM, ROHS COMPLIANT, PLASTIC, MS-022, MQFP-128
文件頁(yè)數(shù)： 10/29頁(yè)
文件大?。?/td> 470K
代理商： ISL98001CQZ-210
10
FN6148.0
October 25, 2005
Pin Descriptions
SYMBOL
MQFP PIN #(s)
DESCRIPTION
R
IN
1
7
Analog input. Red channel 1. DC couple or AC couple through 0.047μF.
G
IN
1
12
Analog input. Green channel 1. DC couple or AC couple through 0.047μF.
B
IN
1
19
Analog input. Blue channel 1. DC couple or AC couple through 0.047μF.
RGB
GND
1
13
Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration.
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
A
.
SOG
IN
1
14
Analog input. Sync on Green. Connect to G
IN
1 through a 0.01μF capacitor in series with a 500
resistor.
HSYNC
IN
1
33
Digital input, 5V tolerant, 240mV hysteresis, 1.2k
impedance to GND
A
. Connect to channel 1's HSYNC
signal through a 680
series resistor.
VSYNC
IN
1
44
Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 1's VSYNC signal.
R
IN
2
22
Analog input. Red channel 2. DC couple or AC couple through 0.047μF.
G
IN
2
24
Analog input. Green channel 2. DC couple or AC couple through 0.047μF.
B
IN
2
28
Analog input. Blue channel 2. DC couple or AC couple through 0.047μF.
RGB
GND
2
25
Analog input. Ground reference for the R, G, and B inputs of channel 2 in the DC coupled configuration.
Connect to the same ground as channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
A
.
SOG
IN
2
26
Analog input. Sync on Green. Connect to G
IN
1 through a 0.01μF capacitor in series with a 500
resistor.
HSYNC
IN
2
34
Digital input, 5V tolerant, 240mV hysteresis, 1.2k
impedance to GND
A
. Connect to channel 2's HSYNC
signal through a 680
series resistor.
VSYNC
IN
2
45
Digital input, 5V tolerant, 500mV hysteresis. Connect to channel 2's VSYNC signal.
CLOCKINV
IN
41
Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180 degrees. Toggle at frame rate
during VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to D
GND
if unused.
RESET
46
Digital input, 5V tolerant, active low, 70k
pullup to V
D
. Take low for at least 1μs and then high again to reset
the ISL98001. This pin is not necessary for normal use and may be tied directly to the V
D
supply.
XTAL
IN
39
Analog input. Connect to external 24.5MHz to 27MHz crystal and load capacitor (See crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
P-P
centered around 0.5V.
XTAL
OUT
40
Analog output. Connect to external 24.5MHz to 27MHz crystal and load capacitor (See crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
P-P
centered around 0.5V.
XCLK
OUT
47
3.3V digital output. Buffered crystal clock output at f
XTAL
or f
XTAL
/2. May be used as system clock for other
system components.
SADDR
48
Digital input, 5V tolerant. Address = 0x4C when tied low. Address = 0x4D when tied high.
SCL
50
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
SDA
49
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
R
P
[7:0]
112-119
3.3V digital output. Red channel, primary pixel data. 56K pulldown when three-stated.
R
S
[7:0]
100-107
3.3V digital output. Red channel, secondary pixel data. 56K pulldown when three-stated.
G
P
[7:0]
90-97
3.3V digital output. Green channel, primary pixel data. 56K pulldown when three-stated.
G
S
[7:0]
80-87
3.3V digital output. Green channel, secondary pixel data. 56K pulldown when three-stated.
B
P
[7:0]
68-75
3.3V digital output. Blue channel, primary pixel data. 56K pulldown when three-stated.
B
S
[7:0]
55-62
3.3V digital output. Blue channel, secondary pixel data. 56K pulldown when three-stated.
DATACLK
121
3.3V digital output. Data clock output. Equal to pixel clock rate in 24-bit mode, one half of pixel clock rate in
48-bit mode.
DATACLK
122
3.3V digital output. Inverse of DATACLK.
HS
OUT
125
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals).
ISL98001
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