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參數(shù)資料
| 型號： | ISL98001 |
| 廠商： | Intersil Corporation |
| 英文描述： | Triple Video Digitizer with Digital PLL |
| 中文描述： | 三路視頻數(shù)字化與數(shù)字鎖相環(huán) |
| 文件頁數(shù)： | 25/29頁 |
| 文件大?。?/td> | 470K |
| 代理商： | ISL98001 |
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25
FN6148.0
October 25, 2005
VS
OUT
VS
OUT
is generated by the ISL98001’s control logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its leading and trailing edges are
aligned with pixel 7 (8 pixels after HSYNC trailing edge). Its
width, in units of lines, is equal to the width of the incoming
VSYNC (See the VSYNC
OUT
description). Its polarity is
determined by register 0x18[6].
This output is not needed in
most applications. Intersil strongly discourages using this
signal - use VSYNC
OUT
instead.
Crystal Oscillator
An external 22MHz to 27MHz crystal supplies the low-jitter
reference clock to the DPLL. The absolute frequency of this
crystal within this range is unimportant, as is the crystal’s
temperature coefficient, allowing use of less expensive,
lower-grade crystals.
As an alternative to a crystal, the XTAL
IN
pin can be driven
with a 3.3V CMOS-level external clock source at any
frequency between 22MHz and 33.5MHz. The ISL98001’s
jitter specification assumes a low-jitter crystal source. If the
external clock source has increased jitter, the sample clock
generated by the DPLL may exhibit increased jitter as well.
EMI Considerations
There are two possible sources of EMI on the ISL98001:
Crystal oscillator.
The EMI from the crystal oscillator is
negligible. This is due to an amplitude-regulated, low voltage
sine wave oscillator circuit, instead of the typical high-gain
square wave inverter-type oscillator, so there are no harmonics.
The crystal oscillator is not a significant source of EMI.
Digital output switching.
This is the largest potential source of
EMI. However, the EMI is determined by the PCB layout and
the loading on the databus. The way to control this is to put
series resistors on the output of all the digital pins (as our demo
board and reference circuits show). These resistors should be
as large as possible, while still meeting the setup and hold
timing requirements of the scaler. We recommend starting with
22
. If the databus is heavily loaded (long traces, many other
part on the same bus), this value may need to be reduced. If
the databus is lightly loaded, it may be increased.
Intersil’s recommendations to minimize EMI are:
Minimize the databus trace length
Minimize the databus capacitive loading.
If EMI is a problem in the final design, increase the value of the
digital output series resistors to reduce slew rates on the bus.
This can only be done as long as the scaler’s setup and hold
timing requirements continue to be met.
Reducing Power Dissipation
It is possible to reduce the total power consumption of the
ISL98001 in applications where power is a concern. There are
several techniques that can be used to reduce power
consumption:
Internal Digital Voltage Regulator.
The ISL98001 features
a 3.3V to 1.9V voltage regulator (pins VREG
IN
and
VREG
OUT
) for the low voltage digital supply. This regulator
typically sources 100mA at 1.9V, dissipating up to 140mW in
heat. Providing an external, clean 1.8V supply to the V
CORE
,
V
PLL
, and V
COREADC
will substantially reduce power
dissipation. The external 1.8V supply should ramp up after
(or at the same time as) the digital 3.3V (V
D
) supply.
Internal Analog Voltage Regulator.
The ISL98001 also
features a 3.3V to 1.9V voltage regulator for the low voltage
analog supply. This voltage appears on the V
BYPASS
pins.
Unlike the digital low voltage supply, there are no “in” and
“out” connections for this regulator. However, this internal
regulator can only source voltage, and can be effectively
bypassed by driving the V
BYPASS
pins with an external, clean
2.0V supply. The external 2.0V supply should ramp up after
(or at the same time as) the analog 3.3V (V
A
) supply.
Buffering Digital Outputs.
Switching 24 or 48 data output
pins into a capacitive bus can consume significant current.
The higher the capacitance on the external databus, the
higher the switching current. To minimize current
consumption inside the ISL98001, minimize bus capacitance
and/or insert data buffers such as the SN64AVC16827
between the ISL98001’s data outputs and the external
databus.
Internal Reference Frequency.
The crystal frequency is
multiplied by the value in register 0x2B to generate an
internal high frequency reference clock. This internal
frequency should be set to 400MHz ±10% for minimum
power consumption. For example, for a 33MHz frequency at
XTAL
IN
, register 0x2B should be set to a value of 0x0C to
minimize power.
Standby Mode
The ISL98001 can be placed into a low power standby mode
by writing a 0x0F to register 0x1B, powering down the triple
ADCs, the DPLL, and most of the internal clocks.
TABLE 6. HS
OUT
WIDTH
HS
OUT
WIDTH (PIXEL CLOCKS)
REGISTER
0x19 VALUE
24-BIT MODE,
RGB
24-BIT MODE,
YPbPr
ALL 48-BIT
MODES
0
0
1
0
1
1
1
0
2
2
3
2
3
3
3
2
4
4
5
4
5
5
5
4
6
6
7
6
7
7
7
6
ISL98001
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