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參數(shù)資料
| 型號： | ISL98001 |
| 廠商： | Intersil Corporation |
| 英文描述： | Triple Video Digitizer with Digital PLL |
| 中文描述： | 三路視頻數(shù)字化與數(shù)字鎖相環(huán) |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 470K |
| 代理商： | ISL98001 |
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11
FN6148.0
October 25, 2005
VS
OUT
126
3.3V digital output. Artificial VSYNC output aligned with pixel data. VS
OUT
is generated 8 pixel clocks after
the trailing edge of HS
OUT
.
This signal is usually not needed.
HSYNC
OUT
127
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC
period. This output will pass composite sync signals and Macrovision signals if present on HSYNC
IN
or
SOG
IN
.
VSYNC
OUT
128
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the
duration of the disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.
V
A
6, 11, 18, 20, 29,
35
Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND
A
with 0.1μF.
GND
A
3, 5, 8, 10, 15,
17, 21, 23, 27,
30, 36
Ground return for V
A
and V
BYPASS
.
V
D
54, 67, 77, 89,
99, 111, 124
Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND
D
with 0.1μF.
GND
D
32, 43, 51, 53,
66, 76, 78, 88,
98, 108, 110,
120, 123
Ground return for V
D
, V
CORE
, V
COREADC
, and V
PLL
.
V
X
38
Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND
X
with 0.1μF.
GND
X
37
Ground return for V
X
.
V
BYPASS
4, 9, 16
Bypass these pins to GND
A
with 0.1μF. Do not connect these pins to each other or anything else.
VREG
IN
65
3.3V input voltage for V
CORE
voltage regulator. Connect to a 3.3V source and bypass to GND
D
with 0.1μF.
VREG
OUT
64
Regulated output voltage for V
PLL
, V
COREADC
and V
CORE
; typically 1.9V. Connect only to V
PLL
, V
COREADC
and V
CORE
and bypass at input pins as instructed below. Do not connect to anything else - this output can
only supply power to V
PLL
, V
COREADC
and V
CORE
.
V
COREADC
31
Internal power for the ADC’s digital logic. Connect to VREG
OUT
through a 10
resistor and bypass to GND
D
with 0.1μF.
V
PLL
42
Internal power for the PLL’s digital logic. Connect to VREG
OUT
through a 10
resistor and bypass to GND
D
with 0.1μF.
V
CORE
52, 79, 109
Internal power for core logic. Connect to VREG
OUT
and bypass each pin to GND
D
with 0.1μF.
NC
1, 2, 63
Reserved. Do not connect anything to these pins.
Pin Descriptions
(Continued)
SYMBOL
MQFP PIN #(s)
DESCRIPTION
ISL98001
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| ISL98001CQZ-240 | 功能描述:IC TRPL VIDEO DIGITIZER 128-MQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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