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參數(shù)資料
| 型號(hào)： | ISL96017WIRT8Z |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | 128-Tap DCP, 16kbit EEPROM, and I2C Serial Interface |
| 中文描述： | 10K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDSO8 |
| 封裝： | 3 X 3 MM, 0.80 MM HEIGHT, 0.65 MM PITCH, ROHS COMPLIANT, PLASTIC, TDFN-8 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 330K |
| 代理商： | ISL96017WIRT8Z |
4
FN8243.1
April 17, 2006
DCP IN RESISTOR MODE
(Measurements between RH and RW with RL not connected)
R
127
(Note 8)
Resistance Offset.
U version - DCP Register set to 7F hex.
Measured between R
H
and R
W
pins.
0
0.5
2
MI
W version - DCP Register set to 7F hex.
Measured between R
H
and R
W
pins.
1
5
MI
TC
R
(Note 11,13)
Resistance Temperature Coefficient
±100
ppm/°C
RDNL
(Note 8,9)
Resistance Differential Non-
Linearity
-0.75
0.75
MI
(Note 1)
RINL
(Note 8,10)
Resistance Integral Non-Linearity
-1
1
MI
(Note 1)
EEPROM SPECS
EEPROM Endurance
1,000,000
Cycles
EEPROM Retention
At 55°C
50
Years
t
WC
(Note 12) Non-Volatile Write Cycle Time
6
12
ms
SERIAL INTERFACE SPECS
V
IL
WP, SDA, and SCL Input Buffer
LOW Voltage
-0.3
0.3*
VDD
V
V
IH
WP, SDA and SCL Input Buffer
HIGH Voltage
0.7*
VDD
VDD
+0.3
V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05*
VDD
V
V
OL
SDA Output Buffer LOW Voltage,
Sinking 4mA
0
0.4
V
Cpin
WP, SDA, and SCL Pin Capacitance
10
pF
f
SCL
SCL Frequency
400
kHz
t
IN
Pulse Width Suppression Time at
SDA and SCL Inputs.
Any pulse narrower than the max spec is
suppressed
50
ns
t
AA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VDD, until
SDA exits the 30% to 70% of VDD window
900
ns
t
BUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VDD during
the following START condition
1300
ns
t
LOW
Clock LOW Time
Measured at the 30% of VDD crossing
1300
ns
t
HIGH
Clock HIGH Time
Measured at the 70% of VDD crossing
600
ns
t
SU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VDD
600
ns
t
HD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VDD to
SCL falling edge crossing 70% of VDD
600
ns
t
SU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VDD
window, to SCL rising edge crossing 30% of
VDD
100
ns
t
HD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VDD to
SDA entering the 30% to 70% of VDD window
0
ns
t
SU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VDD
600
ns
Electrical Specifications
Over recommended operating conditions unless otherwise stated. All voltages with respect to GND.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
ISL96017
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