參數(shù)資料
型號(hào)： ISL9217IRZ
廠商： INTERSIL CORP
元件分類(lèi)： 電源管理
英文描述： 8 to 12 Cell Li-Ion Battery Overcurrent Protection and Analog Front End Chip Set
中文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24
封裝： 4 X 4 MM, ROHS COMPLIANT, PLASTIC, QFN-24
文件頁(yè)數(shù)： 9/33頁(yè)
文件大?。?/td> 645K
代理商： ISL9217IRZ
9
FN6488.1
November 2, 2007
WAKE-UP/SLEEP SPECIFICATIONS
Device WKUP Pin Voltage Threshold
(WKUP pin active HIGH rising edge)
V
WKUP1
WKUP pin rising edge (WKPOL = 1)
Device wakes up and sets WKUP flag
HIGH. (ISL9216 only)
3.5
5.0
6.5
V
Device WKUP Pin Hysteresis
(WKUP pin active HIGH)
V
WKUP1H
WKUP pin falling edge hysteresis
(WKPOL = 1) sets WKUP flag LOW (does
not automatically enter sleep mode)
(ISL9216 only)
100
mV
Internal Resistor on WKUP
R
WKUP
Resistance from WKUP pin to VSS
(WKPOL = 1) (ISL9216 only)
130
230
330
k
Ω
Device WKUP Pin Voltage Threshold
(WKUP pin active LOW - Falling Edge)
V
WKUP2
WKUP pin falling edge (WKPOL = 0)
Device wakes up and sets WKUP flag
HIGH.
V
CELL1
- 2.6 V
CELL1
- 2.0
V
CELL1
- 1.2
V
Device WKUP Pin Hysteresis
(WKUP pin active LOW)
V
WKUP2H
WKUP pin rising edge hysteresis
(WKPOL = 0) sets WKUP flag LOW (does
not automatically enter sleep mode)
200
mV
Device Wake-up Delay
t
WKUP
Delay after voltage on WKUP pin crosses
the threshold (rising or falling) before
activating the WKUP bit.
20
40
60
ms
FET CONTROL SPECIFICATIONS
(For VCELL1, VCELL2, VCELL3 voltages from 2.8V to 4.3V - ISL9216 only)
Control Outputs Response Time
(CFET, DFET)
t
CO
Bit 0 to start of control signal (DFET)
Bit 1 to start of control signal (CFET)
1.0
μs
CFET Gate Voltage
VCFET
No load on CFET
V
CELL3
- 0.5
V
CELL3
- 0.5
80
V
CELL3
V
CELL3
400
V
DFET Gate Voltage
VDFET
No load on DFET
V
FET Turn-on Current (DFET)
I
DF(ON)
I
CF(ON)
I
DF(OFF)
R
DF(OFF)
VDFET <1V (When turning off the FET)
DFET voltage = 0 to VCELL3 - 1.5V
130
μA
FET Turn-on Current (CFET)
CFET voltage = 0 to VCELL3 - 1.5V
80
200
400
μA
FET Turn-off Current (DFET)
DFET voltage = VDFET to 1V
100
180
mA
DFET Resistance to VSS
11
Ω
SERIAL INTERFACE CHARACTERISTICS
(Over recommended operating conditions, unless otherwise specified)
SCL Clock Frequency
f
SCL
t
AA
100
kHz
SCL Falling Edge to SDA Output Data
Valid
From SCL falling crossing V
IH
(min), until
SDA exits the V
IL
(max) to V
IH
(min) window.
SDA crossing V
IH
(min) during a STOP
condition to SDA crossing V
IH
(min) during
the following START condition.
3.5
μs
Time the Bus Must be Free Before Start of
New Transmission
t
BUF
4.7
μs
Clock LOW Time
t
LOW
t
HIGH
t
SU:STA
Measured at the V
IL
(max) crossing.
Measured at the V
IH
(min) crossing.
SCL rising edge to SDA falling edge. Both
crossing the V
IH
(min) level.
From SDA falling edge crossing V
IL
(max) to
SCL falling edge crossing V
IH
(min).
From SDA exiting the V
IL
(max) to V
IH
(min)
window to SCL rising edge crossing
V
IL
(min).
From SCL rising edge crossing V
IH
(min) to
SDA entering the V
IL
(max) to V
IH
(min)
window.
4.7
μs
Clock HIGH Time
4.0
μs
Start Condition Setup Time
4.7
μs
Start Condition Hold Time
t
HD:STA
4.0
μs
Input Data Setup Time
t
SU:DAT
250
ns
Input Data Hold Time
t
HD:DAT
300
ns
Stop Condition Setup Time
t
SU:STO
From SCL rising edge crossing V
IH
(min) to
SDA rising edge crossing V
IL
(max).
4.0
μs
Operating Specifications
All Specifications Apply to Both the ISL9216 and ISL9217 Separately Over the Recommended Operating
Conditions, Unless Otherwise Specified.
(Continued)
DESCRIPTION
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISL9216, ISL9217
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