參數(shù)資料
型號(hào)： ISL9206EVAL1
廠商： Intersil Corporation
英文描述： FlexiHash For Battery Authentication
中文描述： FlexiHash對(duì)于電池認(rèn)證
文件頁(yè)數(shù)： 6/16頁(yè)
文件大?。?/td> 364K
代理商： ISL9206EVAL1
6
FN9260.0
March 9, 2006
OTP ROM
The 16-byte OTP ROM memory is based on EEPROM
technology and is incorporated into the ISL9206 for storage
of non-volatile information. OTP ROM contents (refer to
Table 8) can include but not limited to:
1) Device default settings (address 0-00)
2) Factory programmed trim parameters (address 0-01)
3) Device authentication secrets (address 0-02 to 0-0D)
4) Pack information and ID (address 0-0E and 0-0F)
The memory can be written multiple times before two lock-
out bits (SLO[1:0] in DCFG, see Table 8) being set. The
SLO[1] (bit 1) locks out the memory between 0-02 and 0-09
and the SLO[0] (bit 0) locks out the memory between 0-0A to
0-0D. These two bits can be set independently. Prior to lock-
out, the memory can be written and read directly through the
XSD bus interface. After lock-out, writing to all ROM
addresses and reading from secret code locations will be
permanently disabled after performing a reset cycle.
Writing to the EEPROM requires the supply voltage at the VDD
pin be maintained at a minimum of 2.8V. Failure to do so may
result in unreliable ROM programming or total write failure.
The OTP ROM must be written two bytes at a time, but 2, 4
or 16 bytes of data can be read by the host in a single bus
transaction. Only even addresses are allowed in OTP ROM
read/write. A 16-byte read with CRC allows the entire ROM
content to be quickly verified by simply checking the CRC
byte. The DTRM address stores the default trimming
parameters and is a read-only address. The DCFG and
DTRM (0-00 and 0-01 addresses) need be written
simultaneously but the data to the DRTM address is ignored.
The OTP ROM writing process takes approximately 1.8ms
per two-byte. While the write process is taking place, no bus
transaction is allowed. Attempt to access the ISL9206 during
an on-going write process will result in the device ignoring
the access instruction and issuing an interrupt to the host.
The OTP ROM programming is register-based, and may be
performed at the pack manufacturer’s facility.
Device Control and Status
The ISL9206 has a control and a status register. The control
register can be read and written by the host but the status
register is read only. Both registers contain the device
configuration information (see Table 9). The status register
also contains the device status information that may lead to
an interrupt signal to the host.
Following a host-initiated power-on ‘break’ signal or soft
reset command, the ISL9206 will configure its default mode
of operation based on information stored within DCFG
address of the OTP ROM. The default configuration is
loaded into the master control (MSCR) and the status
(STAT) registers. Functions that are configured by OTP
ROM settings include:
a) device address (DAB[1:0])
b) XSD bus speed (SPD[1:0])
c) register default settings (eINT and ASLP)
d) ROM read/write lock-out (SLO[1:0])
The ISL9206 incorporates interrupt functions to allow the
host to be quickly informed of device status and error
conditions. Available interrupts are summarized in Table 1.
When an interrupt enable bit is set, a ’break’ command is
sent to the host whenever its corresponding interrupt status
bit is set. After this, the host should read the STAT register
immediately. If the following instruction frame from the host
does not access the STAT register, another ‘break’ will be
sent immediately after receiving the full instruction frame.
This process is repeated until the host reads from the STAT
register. Upon reading of the STAT register, all status bits will
be cleared.
Refer to the MSCR and STAT register descriptions for
detailed explanation of the interrupt functions.
FlexiHash+ Engine
The FlexiHash+ engine contains a 32-bit highly non-linear
proprietary hash engine and three registers. Table 10 lists
the three registers. The 1-byte secret selection (SESL)
register select two sets of secret (32-bit each) from the OTP
ROM to program the hash engine. The 4-byte challenge
code register (CHLG) receives the challenge code from the
host through the XSD bus. Once the challenge code is
received, the hash engine generates a 1-byte authentication
result code and stores in the AUTH register for the host to
read. Figure 5 shows the data flow of the authentication
process. The following sections describe the authentication
process and FlexiHash+ encoding scheme in detail.
THE DEVICE AUTHENTICATION PROCESS
To start an authentication process, the host sends a ‘break’
command to wake up the ISL9206. Then host writes to the
SESL register to select the two sets of secrets to be used for
authentication code generation. After that, the host
generates a pseudo-random 4-byte challenge code to input
into the CHLG register to initiate the authentication process.
Upon receiving the fourth byte of the challenge code, the
ISL9206 immediately starts computing the authentication
code. Once the computation is completed, the 8-bit
authentication code is made available at the AUTH register
for the host to read out. The host reads this code and,
concurrently, calculates the correct authentication code
based on the challenge code it generated and the same
secrets chosen, and finally compares the result with the
authentication code read from the device. If the codes do not
match up, the device is a fake device and the host may shut
itself down. The flow chart in Figure 6 summarizes the above
process that the host needs to execute.
ISL9206
相關(guān)PDF資料
PDF描述
ISL9208IRZ Multi-Cell Li-ion Battery Pack OCP/Analog Front End
ISL9209B Charging System Safety Circuit
ISL9209BIRZ Charging System Safety Circuit
ISL9209 Charging System Safety Circuit
ISL9209IRZ Charging System Safety Circuit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISL9208 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Multi-Cell Li-ion Battery Pack OCP/Analog Front End
ISL9208_0711 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Multi-Cell Li-ion Battery Pack OCP/Analog Front End
ISL9208EVAL1Z 制造商:Intersil Corporation 功能描述:ISL9208 EVALUATION BOARD 1 - ROHS COMPLIANT - QFN - Bulk
ISL9208EVAL2Z 功能描述:EVAL BOARD 2 FOR ISL9208 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板
ISL9208IRZ 功能描述:IC MULTI-CELL LI-ION PROT 32-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電池管理 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:Impedance Track™ 功能:燃料，電量檢測(cè)計(jì)/監(jiān)控器 電池化學(xué):鋰離子（Li-Ion） 電源電壓:2.4 V ~ 2.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:帶卷 (TR) 產(chǎn)品目錄頁(yè)面:1020 (CN2011-ZH PDF) 配用:BQ27350EVM-ND - BQ27350EVM 其它名稱:296-21665-2
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*