參數(shù)資料
型號(hào)： ISL88731HRZ-T
廠商： INTERSIL CORP
元件分類： 電源管理
英文描述： SMBus Level 2 Battery Charger
中文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC28
封裝： 5 X 5 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, PLASTIC, TQFN-28
文件頁(yè)數(shù)： 8/22頁(yè)
文件大?。?/td> 474K
代理商： ISL88731HRZ-T
8
FN9258.0
November 20, 2006
Functional Pin Descriptions
BOOT
High-Side Power MOSFET Driver Power-Supply
Connection. Connect a 0.1μF capacitor from BOOT to
PHASE.
UGATE
High-Side Power MOSFET Driver Output. Connect to the
high-side N-channel MOSFET gate.
LGATE
Low-Side Power MOSFET Driver Output. Connect to
low-side N channel MOSFET. LGATE drives between VDDP
and PGND.
PHASE
High-Side Power MOSFET Driver Source Connection.
Connect to the source of the high-side n channel MOSFET.
CSOP
Charge Current-Sense Positive Input.
CSON
Charge Current-Sense Negative Input.
CSSP
Input Current-Sense Positive Input.
CSSN
Input Current-Sense Negative Input.
DCIN
Charger Bias Supply Input. Bypass DCIN with a 0.1μF
capacitor to GND.
ACIN
AC Adapter Detection Input. Connect to a resistor divider
from the AC adapter output.
ACOK
AC Detect Output. This open drain output is high impedance
when ACIN is greater than 3.2V. The ACOK output remains
low when the ISL88731 is powered down. Connect a 10k
pull-up resistor from ACOK to VDDSMB.
ICM
Input Current Monitor Output. ICM voltage equals
20 x (V
CSSP
- V
CSSN
).
PGND
Power Ground. Connect PGND to the source of the low side
MOSFET.
VCC
Power input for internal analog circuits. Connect a 4.7
Ω
resistor from VCC to VDDP and a 1μF ceramic capacitor
from VCC to ground.
VDDP
Linear Regulator Output. VDDP is the output of the 5.2V
linear regulator supplied from DCIN. VDDP also directly
supplies the LGATE driver and the BOOT strap diode.
Bypass with a 1μF ceramic capacitor from VDDP to PGND.
ICOMP
Compensation Point for the charging current and adapter
current regulation Loop. Connect 0.01μF to GND. See the
VCharge Current Control Loop section for details of
selecting the ICOMP capacitor.
VCOMP
Compensation Point for the voltage regulation loop. Connect
4.7k
Ω
in series with 0.01μF to GND. See “VOLTAGE
CONTROL LOOP” on page 19 for details on selecting
VCOMP components.
VFB
Feed Back for the Battery Voltage.
VDDSMB
SMBus interface Supply Voltage Input. Bypass with a 0.1μF
capacitor to GND.
SDA
SMBus Data I/O. Open-drain Output. Connect an external
pull-up resistor according to SMBus specifications.
SCL
SMBus Clock Input. Connect an external pull-up resistor
according to SMBus specifications.
GND
Analog Ground. Connect directly to the backside paddle.
Connect to PGND close to the output capacitor.
Back Side Paddle
Connect the backside paddle to GND.
NC
No Connect. Pins 1, 5, 7 and 14 are not connected.
ISL88731
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