參數(shù)資料
型號(hào)： ISL88731HRZ-T
廠商： INTERSIL CORP
元件分類： 電源管理
英文描述： SMBus Level 2 Battery Charger
中文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC28
封裝： 5 X 5 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, PLASTIC, TQFN-28
文件頁(yè)數(shù)： 20/22頁(yè)
文件大小： 474K
代理商： ISL88731HRZ-T
20
FN9258.0
November 20, 2006
information is added to the feedback to create a second zero
F
ZERO2
. The low pass filter R
F2
, C
F2
between R
S2
and
ISL88731 add a pole at F
FILTER
. R
3
and R
4
are internal
divider resistors that set the DC output voltage. For a 3 cell
battery, R
3
= 500k
Ω
and R
4
= 100k
Ω
. The equations
following relate the compensation network’s poles, zeros
and gain to the components in Figure 23. Figure 25
shows
an asymptotic Bode plot of the DC/DC converter’s gain vs.
frequency. It is strongly recommended that F
ZERO1
is
approximately 30% of F
LC
and F
ZERO2
is approximately 70%
of F
LC
.
FIGURE 25. ASYMPTOTIC BODE PLOT OF THE VOLTAGE
CONTROL LOOP GAIN
Compensation Break Frequency Equations
Choose R
VCOMP
equal or lower than the value calculated
from Equation 29.
Next choose C
VCOMP
equal or higher than the value
calculated from Equation 30.
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown below:
1. Top Layer: signal lines, or half board for signal lines and
the other half board for power lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces.
Component Placement
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT,
traces can be short.
Place the components in such a way that the area under the
IC has less noise traces with high dv/dt and di/dt, such as
gate signals and phase node signals.
FIGURE 24. FREQUENCY RESPONSE OF THE LC OUTPUT
FILTER
P
(
G
FREQUENCY
R
= 200m
Ω
R
= 50m
Ω
NO BATTERY
-60
-40
-20
0
20
40
60
0.1
1
10
100
1000
FREQUENCY (kHz)
G
Compensator
Modulator
Loop
F
F
ZERO1
ZERO2
F
FILTER
F
LC
F
POLE1
F
ESR
F
ZERO1
VCOMP
1COMP
)
----------------------------------------------------------------------
=
(EQ. 23)
F
ZERO2
R
SENSE
o
----------------------------------------------
R
+
R
4
R
3
--------------------
-----------
=
(EQ. 24)
F
LC
2
π
L C
o
(
)
-------------------------------
=
(EQ. 25)
F
FILTER
F2
F2
)
------------------------------------------
=
(EQ. 26)
F
POLE1
SENSE
o
)
---------------------------------------------------
=
(EQ. 27)
F
ESR
o
ESR
)
-------------------------------------------
=
(EQ. 28)
R
VCOMP
0.7 F
LC
(
)
2
π
C
o
R
SENSE
(
)
-----------
R
--------------------
R
4
+
4
(EQ. 29)
=
C
VCOMP
VCOMP
LC
)
--------------------------------------------------------------------------
=
(EQ. 30)
ISL88731
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