參數(shù)資料
型號(hào)： ISL88550AIRZ-T
廠商： INTERSIL CORP
元件分類： 穩(wěn)壓器
英文描述： Synchronous Step Down Controller with Sourcing and Sinking LDO Regulator
中文描述： SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PQCC28
封裝： 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220WHHD-1, TQFN-28
文件頁(yè)數(shù)： 16/25頁(yè)
文件大?。?/td> 928K
代理商： ISL88550AIRZ-T
16
FN6168.0
October 12, 2005
drops 10% below or rises 10% above the nominal regulation
voltage, the ISL88550A pulls POK1 low. Any fault condition
forces POK1 low until the fault latch is cleared by toggling
SHDNA# or cycling AV
DD
power below 1V. For logic level
output voltages, connect an external pull up resistor between
POK1 and AV
DD
. A 100K resistor works well in most
applications. Note that the POK1 window detector is
completely independent of the overvoltage and undervoltage
protection fault detectors and the state of VTTS and VTTR.
SHDNA# and Output Discharge
The SHDNA# input corresponds to the Buck Regulator and
places the Buck Regulator’s portion of the IC in a low power
mode (see Electrical Characteristics Table). SHDNA# is also
used to reset a fault signal such as an overvoltage or
undervoltage fault.
When output discharge is enabled (OVP/UVP = AV
DD
or
open) and SHDNA# is pulled low, or if UVP is enabled
(OVP/UVP = AV
DD
) and V
OUT
falls to 70% of its regulation
set point, the ISL88550A discharges the Buck Regulator
output (via the OUT input) through an internal 15
switch to
ground. While the output is discharging, the PWM controller
is disabled, but the reference remains active to provide an
accurate threshold.
When output discharge is disabled (OVP/UVP = REF or
GND), the controller does not actively discharge the Buck
Output. Under these conditions, the Buck Output discharge
rate is determined by the load current and its output
capacitance. The Buck Regulator detects and latches the
discharge mode state set by OVP/UVP setting on startup.
STBY#
The STBY# input is an active low input that is used to
shutdown only the VTT output. When STBY# is low, VTT is
high impedance, but the VTTR output is still active if
SHDNA# is high. VTT and VTTR are pulled to 0V when
SHDNA is low.
Power OK (POK2)
POK2 is the open-drain output for a window comparator that
continuously monitors the VTTS input and VTTR output.
POK2 is high impedance as long as the output voltage is
within ±10% of the nominal regulation voltage as set by
REFIN. When V
VTTS
or V
VTTR
rise 10% above or 10%
below their nominal regulation voltage, the ISL88550A pulls
POK2 low. For logic level output voltages, connect an
external pull up resistor between POK2 and AV
DD
. A 100K
resistor works well in most applications. Note that the POK2
window detector is completely independent of the
overvoltage and undervoltage protection fault detectors and
the state of VDDQ.
Current Limit (LDO for VTT and VTTR buffer)
The VTT output is a linear regulator that regulates the input
(VTTI) to the V
REFIN
voltage. The feedback point for VTT
is at the VTTS input (see Figure 21 Block Diagram). VTT is
capable of sourcing up to 2.5A and sinking up to -2.0A
continuously. The current limit for VTT and VTTR is typically
+3.0A/-2.5A and ±40mA respectively. When the current limit
for either output is reached, the outputs regulate the current
not the voltage. The current limits for both VTT and VTTR
can be reduced from their full values by forcing the voltage at
the SS pin below 1.6V (typ), or by tying a resistor Rss
between the SS pin and ground such that 4μA*Rss is less
than 1.6V.
POK2 is pulled low when REFIN is < 0.8V.
Fault Protection
The ISL88550A provides overvoltage/undervoltage fault
protection in the buck controller. Select OVP/UVP to enable
and disable fault protection as shown in Table 3. Once
activated, the controller continuously monitors the output for
undervoltage and overvoltage fault conditions. Any VDDQ
shutdown due to OVP, UVP, OTP or SHDNA# = 0 should
also discharge VTT to 0V.
Overvoltage Protection (OVP)
When the output voltage rises above 114% of the nominal
regulation voltage and OVP is enabled (OVP/UVP = AV
DD
or open), the OVP circuit sets the fault latch, shuts down
the PWM controller, and immediately pulls UGATE low
and forces LGATE high. This turns on the synchronous
rectifier MOSFET with 100% duty cycle, rapidly
discharging the output capacitor and clamping the output
to ground. Note that immediately latching LGATE high can
cause the output voltage to go slightly negative due to
energy stored in the output LC circuit at the instant the
OVP occurs. If the load cannot tolerate a negative voltage,
place a power Schottky diode across the output to act as a
reverse polarity clamp. Toggle SHDNA# or cycle AV
DD
power below 1V to clear the fault latch and restart the
controller. OVP is disabled when OVP/UVP is connected
to REF or GND (see Table 3). OVP only applies to the
Buck Output. The VTT and VTTR Outputs do not have
overvoltage protection. When VDDQ is discharged to 0V
due to OVP, VTT is also discharged to 0V.
TABLE 2. SHUTDOWN AND STANDBY CONTROL LOGIC
SHDNA#
STBY#
BUCK
OUTPUT
VTT
VTTR
GND
X
OFF
OFF
(Discharge to
0V)
OFF
(Tracking
REFIN)
AV
DD
GND
ON
OFF
(High
Impedance)
ON
AV
DD
AV
DD
ON
ON
ON
ISL88550A
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