參數(shù)資料
型號(hào)： ISL88550AIRZ-T
廠商： INTERSIL CORP
元件分類： 穩(wěn)壓器
英文描述： Synchronous Step Down Controller with Sourcing and Sinking LDO Regulator
中文描述： SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PQCC28
封裝： 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220WHHD-1, TQFN-28
文件頁(yè)數(shù)： 15/25頁(yè)
文件大?。?/td> 928K
代理商： ISL88550AIRZ-T
15
FN6168.0
October 12, 2005
FIGURE 23. ADJUSTABLE CURRENT LIMIT THRESHOLD
FIGURE 24.
VALLEY CURRENT-LIMIT THRESHOLD
POR, UVLO, and Soft-Start
Internal Power-on reset (POR) occurs when AV
DD
rises
above approximately 2V, resetting the fault latch and the
soft-start counter, powering up the reference, and preparing
the Buck Regulator for operation. Until AV
DD
reaches 4.25V
(typical), AV
DD
undervoltage lockout (UVLO) circuitry inhibits
switching. The controller inhibits switching by pulling UGATE
low and holding LGATE low when OVP and shutdown
discharge are disabled (OVP/UVP = REF or GND) or forcing
LGATE high when OVP and shutdown discharge are
enabled (OVP/UVP = AV
DD
or OPEN). See Table 3 for
detailed truth table for OVP/UVP and Shutdown settings.
When AV
DD
rises above 4.25V, the controller activates the
Buck Regulator and initializes the internal soft start. The
Buck Regulator’s internal soft-start allows a gradual increase
of the current limit level during startup to reduce the input
surge currents. The ISL88550A divides the soft-start period
into five phases. During the first phase, the controller limits
the current limit to only 20% of the full current limit. If the
output does not reach regulation within 425μs, soft start
enters the second phase, and the current limit is increased
by another 20%. This process repeats until the maximum
current limit is reached, after 1.7ms, or when the output
reaches the nominal regulation voltage, whichever occurs
first. Adding a capacitor in parallel with the external ILIM
resistors creates a continuously adjustable analog soft-start
function for the Buck Regulator’s output.
For most applications, LDO soft start is not necessary
because of output charging current is limited to
approximately 3.0A. For 20μF LDO output capacitors, the
minimum rise time is about 30μs. However, soft start in the
LDO section can be realized by tying a capacitor between
the SS pin and ground. When STBY# is driven low, or during
thermal shutdown of the LDO’s, the SS capacitor is
discharged. When STBY# is driven high or when the thermal
limit is removed, an internal 4μA (typ) current charges the
SS capacitor. The resulting linear ramp voltage on SS
linearly increases the current-limit comparator thresholds to
both the VTT and VTTR outputs, until full current limit is
attained when SS reaches approximately 1.6V. This lowering
of the current limit during start-up limits the initial in-rush
current peaks, particularly when driving higher output
capacitances. For good tracking, choose the value of the SS
cap less than 390pF. Leave SS floating to disable the soft-
start feature.
Power OK (POK1)
POK1 is an open-drain output for a window comparator that
continuously monitors V
OUT
. POK1 is actively held low when
SHDNA# is low and during the Buck Regulator outputs soft-
start. After the digital soft-start terminates, POK1 becomes
high impedance as long as the output voltage is within ±10%
of the nominal regulation voltage set by FB. When V
OUT
+
-
+
-
VDD-1V
1.0V
LX
ILIM
ISL88550A
REF
9R
R
RA
RB
CILIM
CREF
ILIMIT
ILOAD
IPEAK
I
ILOAD(MAX)
I
I
LIM VAL
)
I
LOAD
I
2
-----
–
=
ISL88550A
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