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參數(shù)資料
| 型號： | ISL8502 |
| 廠商： | Intersil Corporation |
| 英文描述： | 2.5A Synchronous Buck Regulator with Integrated MOSFETs |
| 中文描述： | 包2.5a同步降壓穩(wěn)壓器，集成的MOSFET |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 526K |
| 代理商： | ISL8502 |
16
FN6389.0
January 17, 2007
The amplitudes of the different types of voltage excursions
can be approximated using Equation 5.
where: I
tran
= Output Load Current Transient and C
out
=
Total Output Capacitance
In a typical converter design, the ESR of the output capacitor
bank dominates the transient response. The ESR and the
ESL are typically the major contributing factors in
determining the output capacitance. The number of output
capacitors can be determined by using Equation 6, which
relates the ESR and ESL of the capacitors to the transient
load step and the voltage limit (DVo):
If DV
SAG
and/or DV
HUMP
are found to be too large for the
output voltage limits, then the amount of capacitance may
need to be increased. In this situation, a trade off between
output inductance and output capacitance may be
necessary.
The ESL of the capacitors, which is an important parameter
in the above equations, is not usually listed in databooks.
Practically, it can be approximated using Equation 7 if an
Impedance Vs. Frequency curve is given for a specific
capacitor:
where: f
res
is the frequency where the lowest impedance is
achieved (resonant frequency).
The ESL of the capacitors becomes a concern when
designing circuits that supply power to loads with high rates
of change in the current.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by using Equation 8:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL8502 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. Equation 9 gives
the approximate response time interval for application and
removal of a transient load:
where: I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time the upper MOSFET
turns on. Place the small ceramic capacitors physically close
to the MOSFETs and between the drain of the upper
MOSFET and the source of the lower MOSFET.
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current through the input capacitors
may be closely approximated using Equation 10:
Δ
V
ESR
ESR
I
tran
=
Δ
V
ESL
ESL
dI
-----dt
=
Δ
V
SAG
L
I
in
2
out
out
)
-------------------------------–
=
Δ
V
HUMP
L
out
I
out
2
--------------------------------
=
(EQ. 5)
Number of Caps
ESL
---------------------------------
-----------------------------------------------------------------------
dI
ESR
I
+
o
=
(EQ. 6)
ESL
C 2
π
f
res
)
2
-------------------1
=
(EQ. 7)
Δ
I
=
V
IN
- V
OUT
Fs x L
V
OUT
V
IN
Δ
V
OUT
=
Δ
I
x
ESR
x
(EQ. 8)
t
RISE
=
L x I
TRAN
V
IN
- V
OUT
t
FALL
=
L x I
TRAN
V
OUT
(EQ. 9)
V
IN
-------------
I
OUTMAX
2
1
V
IN
-------------
–
×
1
12
------
V
V
OSC
–
----------------------------
V
IN
-------------
×
2
×
+
×
(EQ. 10)
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