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參數(shù)資料
| 型號： | ISL8502 |
| 廠商： | Intersil Corporation |
| 英文描述： | 2.5A Synchronous Buck Regulator with Integrated MOSFETs |
| 中文描述： | 包2.5a同步降壓穩(wěn)壓器，集成的MOSFET |
| 文件頁數(shù)： | 13/19頁 |
| 文件大小： | 526K |
| 代理商： | ISL8502 |
13
FN6389.0
January 17, 2007
Functional Pin Description
PGOOD (Pin 1)
PGOOD is an open drain output that will pull to low if the
output goes out of regulation or a fault is detected. PGOOD
is equipped with a fixed delay upon output power-up. The
delay is approximately 250ms at switching frequency
500kHz and 108ms at 1.2MHz.
SGND (Pin 2)
The SGND terminal of the ISL8502 provides the return path
for the control and monitor portions of the IC.
EN (Pin 3)
The Enable pin is a bidirectional pin. If the voltage on this pin
exceeds the enable threshold voltage, the part is enabled. If
a fault is detected, the EN pin will be pulled low via internal
circuitry for a duration of 4 soft-start periods. For automatic
start-up, use 10k
Ω
to 100k
Ω
pull up resistor connecting to
VCC.
SYNCH (Pin 4)
This is a bidirectional pin that is used to synchronize slave
devices to the Master device. As a Master device, this pin
outputs the clock signal that the slave devices use to
synchronize to. As a slave device, this pin is an input to
receive the clock signal from the master device.
If configured as a slave device, the ISL8502 will be disabled
if there is no clock signal from the master device on the
SYNCH pin.
Leave this pin unconnected if the IC is used in stand alone
operation.
M/S (Pin 5)
As a slave device, tie a 5k
Ω
resistor between this pin and
ground.
As a master or a stand alone device, tie this pin directly to
the VCC pin. Do not short M/S pin to GND.
FS (Pin 6)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
T
) from this pin to GND, the switching
frequency can be programmed as desired between 500kHz
and 1.2MHz.
Tying the FS pin to the VCC pin will force the switching
frequency to 800kHz.
Using resistors with values below 40k
Ω
(1.2MHz) or with
values higher than 97k
Ω
(500kHz) may damage the
ISL8502.
COMP (Pin 7) and FB (Pin 8)
The switching regulator employs a single voltage control
loop. FB is the negative input to the voltage loop error
amplifier. The output voltage is set by an external resistor
divider connected to FB. With a properly selected divider, the
output voltage can be set to any voltage between the power
rail (reduced by converter losses) and the 0.6V reference.
Loop compensation is achieved by connecting an AC
network across COMP and FB.
The FB pin is also monitored for undervoltage events.
SS (Pin 9)
Connect a capacitor from this pin to ground. This capacitor,
along with an internal 30
μ
A current source, sets the soft-start
interval of the converter, T
SS
.
PGND (Pins 10-13)
These pins are used as the ground connection of the power
train.
PHASE (Pins 14-17)
These pins are the PHASE node connections to the inductor.
These pins are connected the source of the control
MOSFET and the drain of the synchronous MOSFET.
VIN (Pins 18-21)
Connect the input rail to these pins. These pins are the input
to the regulator as well as the source for the internal linear
regulator that supplies the bias for the IC.
It is recommended that the DC voltage applied to the VIN
pins does not exceed 14V. This recommendation allows for
transient spikes and voltage ringing to occur while not
exceeding Absolute Maximum Ratings.
BOOT (Pin 22)
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive the internal N-channel MOSFET.
The boot diode is included within the ISL8502.
PVCC (Pin 23)
This pin is the output of the internal linear regulator that
supplies the bias and gate voltage for the IC. A minimum
4.7
μ
F decoupling capacitor is recommended.
VCC (Pin 24)
This pin supplies the bias voltage for the IC. This pin should
be tied to the PVCC pin through an RC low pass filter. A 10
Ω
resistor and 0.1
μ
F capacitor is recommended.
R
T
k
Ω
[
]
OSC
]
------------------------------
=
(EQ. 1)
C
SS
μ
F
[
]
50 T
SS
S
[ ]
=
(EQ. 2)
ISL8502
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