參數(shù)資料
型號(hào)： ISL8102EVAL1
廠商： Intersil Corporation
英文描述： Two-Phase Buck PWM Controller with High Current Integrated MOSFET Drivers
中文描述： 兩相降壓PWM控制器，帶有高電流集成MOSFET驅(qū)動(dòng)器
文件頁(yè)數(shù)： 21/27頁(yè)
文件大?。?/td> 711K
代理商： ISL8102EVAL1
21
FN9247.0
October 19, 2005
yields a solution that is always stable with very close to ideal
transient performance.
The feedback resistor, R
1
, has already been chosen as
outlined in
Load-Line Regulation Resistor.
Select a target
bandwidth for the compensated system, F
0
. The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
compensation components depend on the relationships of f
0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
In Equations 28, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent series
resistance of the bulk output filter capacitance; and V
OSC
is
the peak-to-peak sawtooth signal amplitude as described in
the
Electrical Specifications
.
Once selected, the compensation values in Equations 28
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R
2
. Slowly increase the
value of R
2
while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C
1
will not need adjustment. Keep the value of C
1
from
Equations 28 unless some performance issue is noted.
The optional capacitor C
2
, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 20). Keep
a position available for C
2
, and be prepared to install a high
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
Compensating the Converter operating without
Load-Line Regulation
The ISL8102 multi-phase converter operating without load
line regulation behaves in a similar manner to a voltage-
mode controller. This section highlights the design
consideration for a voltage-mode controller requiring external
compensation. To address a broad range of applications, a
type-3 feedback network is recommended (see Figure 21).
Figure 22 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable, with a
small number of adjustments, to the multi-phase ISL8102
circuit. The output voltage (V
OUT
) is regulated to the
reference voltage, VREF, level. The error amplifier output
(COMP pin voltage) is compared with the oscillator (OSC)
modified saw-tooth wave to provide a pulse-width modulated
wave with an amplitude of V
IN
at the PHASE node. The
PWM wave is smoothed by the output filter (L and C). The
output filter capacitor bank’s equivalent series resistance is
represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
COMP
. This function is dominated by a
DC gain, given by d
MAX
V
IN
/V
OSC
, and shaped by the
output filter, with a double pole break frequency at F
LC
and a
zero at F
CE
. For the purpose of this analysis, L and DCR
represent the individual channel inductance and its DCR
divided by 2 (equivalent parallel value of the two output
inductors), while C and ESR represents the total output
capacitance and its equivalent series resistance.
2
π
L C
-----------1
F
0
>
R
2
R
1
2
π
F
V
IN
0.66 V
π
V
OSC
R
1
f
0
L C
-----------------0.66 V
=
C
1
2
=
Case 1:
2
π
L C
-----------1
F
0
π
C ESR
2
<
≤
R
2
R
1
V
---------------------------------------------------------------
2
π
(
)
2
F
2
L C
0.66 V
IN
0.66 V
=
C
1
2
π
(
)
F
0
V
OSC
R
1
L C
-------------------------------------------------------------------------------
=
Case 2:
(EQ. 28)
F
0
2
π
C ESR
---------------1
>
R
2
R
1
2
π
F
V
L
0.66 V
IN
ESR
-----------------------------------------------
=
C
2
0.66 V
ESR
2
π
V
OSC
R
1
F
0
L
------------------------------------------------------C
=
Case 3:
FIGURE 21. COMPENSATION CONFIGURATION FOR
NON-LOAD-LINE REGULATED ISL8102 CIRCUIT
ISL8102
COMP
C
1
R
2
R
1
FB
VDIFF
C
2
R
3
C
3
F
LC
2
π
L C
---------------------------
=
F
CE
---------------------------------
=
ISL8102
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