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參數(shù)資料
| 型號： | ISL6752AAZA-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control |
| 中文描述： | 0.1 A DUAL SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, QSOP-16 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 436K |
| 代理商： | ISL6752AAZA-T |
8
FN9181.1
March 10, 2005
Pin Descriptions
VDD -
VDD is the power connection for the IC. To optimize
noise immunity, bypass VDD to GND with a ceramic
capacitor as close to the VDD and GND pins as possible.
VDD is monitored for supply voltage undervoltage lock-out
(UVLO). The start and stop thresholds track each other
resulting in relatively constant hysteresis.
GND -
Signal and power ground connections for this device.
Due to high peak currents and high frequency operation, a
low impedance layout is necessary. Ground planes and
short traces are highly recommended.
VREF -
The 5.00V reference voltage output having 3%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1
μ
F to 2.2
μ
F low ESR capacitor.
CT -
The oscillator timing capacitor is connected between
this pin and GND. It is charged through an internal 200
μ
A
current source and discharged with a user adjustable current
source controlled by RTD.
RTD -
This is the oscillator timing capacitor discharge
current control pin. The current flowing in a resistor
connected between this pin and GND determines the
magnitude of the current that discharges CT. The CT
discharge current is nominally 20x the resistor current. The
PWM deadtime is determined by the timing capacitor
discharge duration. The voltage at RTD is nominally 2.00V.
CS -
This is the input to the overcurrent comparator. The
overcurrent comparator threshold is set at 1.00 V nominal.
The CS pin is shorted to GND at the termination of either
PWM output.
Depending on the current sensing source impedance, a
series input resistor may be required due to the delay
between the internal clock and the external power switch.
This delay may result in CS being discharged prior to the
power switching device being turned off.
OUTUL and OUTUR -
These outputs control the upper
bridge FETs and operate at a fixed 50% duty cycle in
alternate sequence. OUTUL controls the upper left FET and
OUTUR controls the upper right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the lower FET outputs, OUTLL and OUTLR.
RESDEL -
Sets the resonant delay period between the
toggle of the upper FETs and the turn on of either of the
lower FETs. The voltage applied to RESDEL determines
when the upper FETs switch relative to a lower FET turning
on. Varying the control voltage from 0 to 2.00V increases the
resonant delay duration from 0 to 100% of the deadtime. The
control voltage divided by 2 represents the percent of the
deadtime equal to the resonant delay. In practice the
maximum resonant delay must be set lower than 2.00V to
ensure that the lower FETs, at maximum duty cycle, are OFF
prior to the switching of the upper FETs.
OUTLL and OUTLR -
These outputs control the lower
bridge FETs, are pulse width modulated, and operate in
alternate sequence. OUTLL controls the lower left FET and
OUTLR controls the lower right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the upper FET outputs, OUTUL and
OUTUR.
OUTLLN and OUTLRN -
These outputs are the
complements of the PWM (lower) bridge FETs. OUTLLN is
the complement of OUTLL and OUTLRN is the complement
of OUTLR. These outputs are suitable for control of
synchronous rectifiers. The phase relationship between
each output and its complement is controlled by the voltage
applied to VADJ.
VADJ -
A 0 - 5V control voltage applied to this input sets the
relative delay or advance between OUTLL/OUTLR and
OUTLLN/OUTLRN. The phase relationship between
OUTUL/OUTUR and OUTLL/OUTLR is maintained
regardless of the phase adjustment between OUTLL/OUTLR
and OUTLLN/OUTLRN.
FIGURE 3. DEADTIME (DT) vs CAPACITANCE
FIGURE 4. CAPACITANCE vs FREQUENCY
Typical Performance Curves
(Continued)
0
10
20
30
40
50
60
70
80
90
100
10
100
RTD (k
)
D
CT =
1000pF
680pF
470pF
330pF
220pF
100pF
1-10
4
1-10
3
0.1
1
10
10
100
CT (nF)
F
RTD =
10k
50k
100k
1-10
3
ISL6752
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| ISL6752AAZA-TR5325 | 制造商:Intersil Corporation 功能描述:ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control |
| ISL6752DBEVAL1Z | 功能描述:BOARD DEMO FOR ISL6752 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - DC/DC 與 AC/DC（離線）SMPS 系列:* 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:DC/DC，步降 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:3.3V 電流 - 輸出:3A 輸入電壓:4.5 V ~ 28 V 穩(wěn)壓器拓撲結(jié)構(gòu):降壓 頻率 - 開關(guān):250kHz 板類型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名稱:497-12113STEVAL-ISA094V1-ND |
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