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參數(shù)資料
| 型號(hào)： | ISL6752AAZA-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control |
| 中文描述： | 0.1 A DUAL SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, QSOP-16 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大?。?/td> | 436K |
| 代理商： | ISL6752AAZA-T |
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13
FN9181.1
March 10, 2005
parasitic capacitance in the circuit including winding
capacitance. Each switch is designated by its position, upper
left (UL), upper right (UR), lower left (LL), and lower right
(LR). The beginning of the cycle, shown in Figure 10, is
arbitrarily set as having switches UL and LR on and UR and
LL off. The direction of the primary and secondary currents
are indicated by I
P
and I
S
, respectively.
The UL - LR power transfer period terminates when switch
LR turns off as determined by the PWM. The current flowing
in the primary cannot be interrupted instantaneously, so it
must find an alternate path. The current flows into the
parasitic switch capacitance of LR and UR which charges
the node to VIN and then forward biases the body diode of
upper switch UR.
The primary leakage inductance, L
L
, maintains the current
which now circulates around the path of switch UL, the
transformer primary, and switch UR. When switch LR opens,
the output inductor current free-wheels through both output
diodes, D1 and D2. This condition persists through the
remainder of the half-cycle.
During the period when CT discharges, also referred to as
the deadtime, the upper switches toggle. Switch UL turns off
and switch UR turns on. The actual timing of the upper
switch toggle is dependent on RESDEL which sets the
resonant delay. The voltage applied to RESDEL determines
how far in advance the toggle occurs prior to a lower switch
turning on. The ZVS transition occurs after the upper
switches toggle and before the diagonal lower switch turns
on. The required resonant delay is 1/4 of the period of the LC
resonant frequency of the circuit formed by the leakage
inductance and the parasitic capacitance. The resonant
transition may be estimated from Equation 25.
where
τ
is the resonant transition time, L
L
is the leakage
inductance, C
P
is the parasitic capacitance, and R is the
equivalent resistance in series with L
L
and C
P
.
The resonant delay is always less than or equal to the
deadtime and may be calculated using the following
equation.
where
τ
resdel
is the desired resonant delay, V
resdel
is a
voltage between 0 and 2V applied to the RESDEL pin, and
DT is the deadtime (see Equations 1 - 5).
When the upper switches toggle, the primary current that
was flowing through UL must find an alternate path. It
charges/discharges the parasitic capacitance of switches UL
and LL until the body diode of LL is forward biased. If
RESDEL is set properly, switch LL will be turned on at this
time.
The second power transfer period commences when switch
LL closes. With switches UR and LL on, the primary and
secondary currents flow as indicated below.
The UR - LL power transfer period terminates when switch
LL turns off as determined by the PWM. The current flowing
FIGURE 10. UL - LR POWER TRANSFER CYCLE
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
I
P
I
S
L
L
D2
D1
FIGURE 11. UL - UR FREE-WHEELING PERIOD
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
I
P
I
S
L
L
D2
D1
τ
π
2
--
L
P
--------------
2
---------
4L
L
2
–
-----------------------------------
=
(EQ. 25)
τ
resdel
V
2
-------------------
DT
=
S
(EQ. 26)
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
L
L
D2
D1
I
S
I
P
FIGURE 12. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
L
L
D2
D1
FIGURE 13. UR - LL POWER TRANSFER CYCLE
ISL6752
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