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參數(shù)資料
| 型號： | ISL6752AAZA-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control |
| 中文描述： | 0.1 A DUAL SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, LEAD FREE, PLASTIC, QSOP-16 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 436K |
| 代理商： | ISL6752AAZA-T |
10
FN9181.1
March 10, 2005
The values of R and C should be selected to control the rate
of rise of VERR to the desired soft-start duration. The soft-
start duration may be calculated from Equation. 6.
where V
SS
is the soft-start clamp voltage, V
be
is the base-
emitter voltage drop of the transistor, and
β
is the DC gain of
the transistor. If
β
is sufficiently large, that term may be
ignored. The schottky diode discharges the soft-start
capacitor so that the circuit may be reset quickly.
Gate Drive
The ISL6752 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
totem pole drivers. The typical on resistance of the outputs is
50
.
Overcurrent Operation
The cycle-by-cycle peak current control results in pulse-by-
pulse duty cycle reduction when the current feedback signal
exceeds 1.0V. When the peak current exceeds the
threshold, the active output pulse is immediately terminated.
This results in a well controlled decrease in output voltage as
the load current increases beyond the current limit threshold.
The ISL6752 will operate continuously in an overcurrent
condition.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased
by the leading edge blanking (LEB) interval. The effective
delay is the sum of the two delays and is nominally 105ns.
Slope Compensation
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be
accomplished by summing an external ramp with the current
feedback signal or by subtracting the external ramp from the
voltage feedback error signal. Adding the external ramp to
the current feedback signal is the more popular method.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is
where Sn is the slope of the sawtooth signal and Tsw is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes
where Se is slope of the external ramp and
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
oscillator frequency. The double-pole will be critically
damped if the Q-factor is set to 1, and over-damped for
Q > 1, and under-damped for Q < 1. An under-damped
condition can result in current loop instability.
where D is the percent of on time during a half cycle. Setting
Q = 1 and solving for Se yields
Since S
n
and S
e
are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by T
ON
to obtain the voltage change that occurs during T
ON
.
where V
n
is the change in the current feedback signal during
the on time and V
e
is the voltage that must be added by the
external ramp.
V
n
can be solved for in terms of input voltage, current
transducer components, and output inductance yielding
T
V
CT
O
P
where R
CS
is the current sense burden resistor, N
CT
is the
current transformer turns ratio, L
O
is the output inductance,
V
O
is the output voltage, and N
S
and N
P
are the secondary
and primary turns, respectively.
FIGURE 5. IMPLEMENTING SOFT-START
VREF
1
2
4
3
5
6
7
8
9
10
11
12
13
14
15
16
ISL6752
VERR
R
C
t
RC
–
1
V
V
–
VREF
-------------------
+
-------------------------------------------
–
ln
=
S
(EQ. 6)
Fm
-------------------
=
(EQ. 7)
Fm
)
Tsw
------------+
c
---------------------------
=
=
(EQ. 8)
m
c
1
-------
+
=
(EQ. 9)
Q
c
D
)
0.5
–
)
----------------------–
=
(EQ. 10)
S
e
S
n
1
π
--
0.5
+
D
-----–
1
–
=
(EQ. 11)
V
e
V
n
1
π
--
0.5
+
D
-----–
1
–
=
(EQ. 12)
V
e
R
-----------------------------------------
N
S
-------
1
π
--
D
0.5
–
+
=
V
(EQ. 13)
ISL6752
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參數(shù)描述 |
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| ISL6752AAZA-TR5325 | 制造商:Intersil Corporation 功能描述:ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control |
| ISL6752DBEVAL1Z | 功能描述:BOARD DEMO FOR ISL6752 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - DC/DC 與 AC/DC（離線）SMPS 系列:* 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:DC/DC，步降 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:3.3V 電流 - 輸出:3A 輸入電壓:4.5 V ~ 28 V 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):降壓 頻率 - 開關(guān):250kHz 板類型:完全填充 已供物品:板 已用 IC / 零件:L7981 其它名稱:497-12113STEVAL-ISA094V1-ND |
| ISL6752EVAL1Z | 功能描述:EVALUATION BOARD FOR ISL6752 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| ISL6753AAZA | 功能描述:IC REG CTRLR PWM CM/VM 16-QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6753AAZA-T | 功能描述:IC REG CTRLR PWM CM/VM 16-QSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
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