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參數(shù)資料
| 型號： | ISL6752 |
| 廠商： | Intersil Corporation |
| 英文描述： | Octal Buffers/Drivers With 3-State Outputs 20-PDIP -40 to 85 |
| 中文描述： | ZVS全橋電流模式PWM可調(diào)的同步整流控制 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 436K |
| 代理商： | ISL6752 |
14
FN9181.1
March 10, 2005
in the primary must find an alternate path. The current flows
into the parasitic switch capacitance which charges the node
to VIN and then forward biases the body diode of upper
switch UL. The primary leakage inductance, L
L
, maintains
the current, which now circulates around the path of switch
UR, the transformer primary, and switch UL. When switch LL
opens, the output inductor current free-wheels through both
output diodes, D1 and D2. This condition persists through
the remainder of the half-cycle.
When the upper switches toggle, the primary current that
was flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR
and LR until the body diode of LR is forward biased. If
RESDEL is set properly, switch LR will be turned on at this
time.
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires
that the leakage inductance has sufficient energy stored to
fully charge the parasitic capacitances. Since the energy
stored is proportional to the square of the current (1/2 L
L
I
P2
,
the ZVS resonant transition is load dependent. If the leakage
inductance is not able to store sufficient energy for ZVS, a
discrete inductor may be added in series with the
transformer primary.
Synchronous Rectifier Outputs and Control
The ISL6752 provides double-ended PWM outputs, OUTLL
and OUTLR, and synchronous rectifier (SR) outputs,
OUTLLN and OUTLRN. The SR outputs are the
complements of the PWM outputs. It should be noted that
the complemented outputs are used in conjunction with the
opposite PWM output, i.e. OUTLL and OUTLRN are paired
together and OUTLR and OUTLLN are paired together.
Referring to Figure 16, the SRs alternate between being
both on during the free-wheeling portion of the cycle
(OUTLL/LR off), and one or the other being off when OUTLL
or OUTLR is on. If OUTLL is on, its corresponding SR must
also be on, indicating that OUTLRN is the correct SR control
signal. Likewise, if OUTLR is on, its corresponding SR must
also be on, indicating that OUTLLN is the correct SR control
signal.
A useful feature of the ISL6752 is the ability to vary the
phase relationship between the PWM outputs (OUTLL, OUT
LR) and the their complements (OUTLLN, OUTLRN) by
±300ns. This feature allows the designer to compensate for
differences in the propagation times between the PWM FETs
and the SR FETs. A voltage applied to VADJ controls the
phase relationship.
FIGURE 14. UR - UL FREE-WHEELING PERIOD
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
I
P
I
S
L
L
D2
D1
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
I
P
I
S
L
L
D2
D1
FIGURE 15. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
FIGURE 16. BASIC WAVEFORM TIMING
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 17. WAVEFORM TIMING WITH PWM OUTPUTS
DELAYED, 0V < VADJ < 2.425V
CT
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
ISL6752
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|---|---|
| ISL6752AAZA-T | ZVS Full-Bridge Current-Mode PWM with Adjustable Synchronous Rectifier Control |
| ISL6752AAZA | Octal Buffers/Drivers With 3-State Outputs 20-PDIP -40 to 85 |
| ISL6753 | Octal Buffers/Drivers With 3-State Outputs 20-SO -40 to 85 |
| ISL6753AAZA-T | ZVS Full-Bridge PWM Controller |
| ISL6753AAZA | Octal Buffers/Drivers With 3-State Outputs 20-SO -40 to 85 |
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