參數(shù)資料
型號(hào): ISL6721ABZ
廠商: INTERSIL CORP
元件分類(lèi): 穩(wěn)壓器
英文描述: 1024 x 9 x 2 Asynchronous Bidirectional FIFO Memory 44-PLCC 0 to 70
中文描述: 1 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16
封裝: 0.150 INCH, ROHS COMPLIANT, PLASTIC, MS-012AC, SOIC-16
文件頁(yè)數(shù): 16/20頁(yè)
文件大小: 481K
代理商: ISL6721ABZ
16
the remaining pole and zero for the compensator are located
at:
The ratio of R15 to the parallel combination of R17 and R18
determine the mid band gain of the error amplifier.
From (EQ. 27), it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitance, and
the output capacitance ESR. These variations must be
considered when compensating the control loop. The worst
case small signal operating point for the converter is at
minimum Vin, maximum load, maximum Cout, and minimum
ESR.
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the
bandwidth to about Fsw/4. For this example, the bandwidth
will be further limited due to the low GBWP of the LM431-
based Error Amplifier and the opto-coupler. A bandwidth of
approximately 5kHz was selected.
For the EA compensation, the first pole is placed at the origin
by default (C14 is an integrating capacitor). The first zero is
placed below the crossover frequency, f
co
, usually around
1/3 f
co
. The second pole is placed at the lower of the ESR
zero or at one half of the switching frequency. The midband
gain is then adjusted to obtain the desired crossover
frequency. If the phase margin is not adequate, the
crossover frequency may have to be reduced.
Using this technique to determine the compensation, the
following values for the EA components were selected.
R17 = R18 = R15 = 1k
R20 = open
C13 = 100nF
C14 = 100pF
A Bode plot of the closed loop system at low line, max load
appears below.
f
pc
C
R
15
C
14
2
π
C
13
---------------------------+
2
π
R
15
C
14
--------------------------------------------
=
(EQ. 28)
f
zc
2
π
R
15
C
13
--------------------------------------------
=
(EQ. 29)
A
midband
R
-----------------------------------------------
R
R
+
(
)
R
17
R
18
=
(EQ. 30)
0.01
0.1
Frequency (kHz)
1
10
100
50
40
-50
30
-40
20
-30
10
-20
0
10
20
30
40
50
G
FIGURE 9A. GAIN
50
40
30
20
10
0
-10
G
FIGURE 9B. PHASE MARGIN
0.01
0.1
Frequency (kHz)
1
1
10
100
100
50
0
50
100
150
200
P
0
P
ISL6721
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PDF描述
ISL6721AV 1024 x 9 x 2 Asynchronous Bidirectional FIFO Memory 64-TQFP 0 to 70
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