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參數(shù)資料
| 型號： | ISL6721ABZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1024 x 9 x 2 Asynchronous Bidirectional FIFO Memory 44-PLCC 0 to 70 |
| 中文描述： | 1 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, MS-012AC, SOIC-16 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 481K |
| 代理商： | ISL6721ABZ |
15
A block diagram of the feedback control loop follows in
Figure 7.
The loop compensation is placed around the Error Amplifier
(EA) on the secondary side of the converter. The primary
side amplifier located in the control IC is used as a unity gain
inverting amplifier and provides no loop compensation. A
Type 2 error amplifier configuration was selected as a
precaution in case operation in continuous mode should
occur at some operating point.
Development of a small signal model for current mode
control is rather complex. The method of reference [1] was
selected for its ability to accurately predict loop behavior. To
further simplify the analysis, the converter will be modeled
as a single output supply with all of the output capacitance
reflected to the 3.3V output. Once the “single” output system
is compensated, adjustments to the compensation will be
required based on actual loop measurements.
The first parameter to determine is the peak current
feedback loop gain. Since this application is low power, a
resistor in series with the source of the power switching
MOSFET is used for the current feedback signal. For higher
power applications, a resistor would dissipate too much
power and current transformer would be used instead.
There is limited flexibility to adjust the current loop behavior
due to the need to provide over current protection. Current
limit and the current loop gain are determined by the current
sense resistor and the ISET threshold. ISET was set at 1.0V,
near its maximum, to minimize noise effects. When
determining ISET, the internal gain and offset of the ISENSE
signal in the control IC must be taken into account. The
maximum peak primary current was determined earlier to be
1.87A, so a choice of 2.25A peak primary current for current
limit is reasonable. A current gain, A
EXT
, of 0.5 V/A was
selected to achieve this.
The control to output transfer function may be represented
as [2]
s
ω
z
s
ω
p
if we ignore the current feedback sampled-data effects.
The value of K may be determined by assuming all of the
output power is delivered by the 3.3V output at the threshold
of current limit. The maximum power allowed was
determined earlier as 15 watts, so
where A
EXT
is the external gain of the current feedback
network, A
CS
is the IC internal gain, and A
COMP
is the gain
between the error amplifier and the PWM comparator.
The Type 2 compensation configuration has two poles and
one zero. The first pole is at the origin, and provides the
integration characteristic which results in excellent DC
regulation. Referring to the Typical Application Schematic,
+
-
PWM
POWER
STAGE
Z
3
Z
4
Z
1
Z
2
REF
REF
+
-
ISOLATION
ERROR AMPLIFIER
PRIMARY SIDE AMPLIFIER
V
OUT
FIGURE 7.
REF
+
-
Vout
Verror
FIGURE 8. TYPE 2 ERROR AMPLIFIER
ISET
2.25
0.8
0.5
0.100
+
1.00
=
=
V
(EQ. 26)
v
o
v
c
-----
K
R
-----------------------------------
L
F
1
----------------
------
+
1
------
+
=
(EQ. 27)
K
I
c max
)
)
-------------------------
=
R
o
LoadResis
ce
tan
=
L
s
SecondaryInduc
ce
tan
=
ω
p
o
o
--------------------
=
or
f
p
o
o
-----------------------------
=
ω
z
c
o
-------------------
=
or
f
z
c
2
o
--------------------------------------
=
C
o
OutputCapaci
ce
tan
=
R
c
OutputCapaci
ceE
tan
SR
=
V
c max
)
ControlVoltageRange
=
I
spk max
(
)
2
--------------------------------------
P
-----------
Tsw
2
-----------------------------------------
-------
5
6
–
×
10
2.33
×
10
19.5
=
=
=
A
v
c max
(
)
V
ISENSE
A
EXT
A
CS
COMP
--------------------
2.93
=
=
V
ISL6721
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