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參數(shù)資料
| 型號(hào)： | ISL6594ACBZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 功率晶體管 |
| 英文描述： | Dual Low-Noise Wide-Bandwidth Precision Amplifier 8-TSSOP -40 to 85 |
| 中文描述： | 3 A HALF BRDG BASED MOSFET DRIVER, PDSO8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 306K |
| 代理商： | ISL6594ACBZ-T |
6
FN9157.1
May 6, 2005
Description
Operation
Designed for versatility and speed, the ISL6594A and
ISL6594B MOSFET drivers control both high-side and low-
side N-Channel FETs of a half-bridge power train from one
externally provided PWM signal.
Prior to VCC exceeding its POR level, the Pre-POR
overvoltage protection function is activated during initial
startup; the upper gate (UGATE) is held low and the lower
gate (LGATE), controlled by the Pre-POR overvoltage
protection circuits, is connected to the PHASE. Once the
VCC voltage surpasses the VCC Rising Threshold (See
Electrical Specifications), the PWM signal takes control of
gate transitions. A rising edge on PWM initiates the turn-off
of the lower MOSFET (see Timing Diagram). After a short
propagation delay [t
PDLL
], the lower gate begins to fall.
Typical fall times [t
FL
] are provided in the Electrical
Specifications section. Adaptive shoot-through circuitry
monitors the LGATE voltage and determines the upper gate
delay time [t
PDHU
]. This prevents both the lower and upper
MOSFETs from conducting simultaneously. Once this delay
period is complete, the upper gate drive begins to rise [t
RU
]
and the upper MOSFET turns on.
A falling transition on PWM results in the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t
PDLU
] is encountered before the upper
gate begins to fall [t
FU
]. Again, the adaptive shoot-through
circuitry determines the lower gate delay time, t
PDHL
. The
PHASE voltage and the UGATE voltage are monitored, and
the lower gate is allowed to rise after PHASE drops below a
level or the voltage of UGATE to PHASE reaches a level
depending upon the current direction (See next section for
details). The lower gate then rises [t
RL
], turning on the lower
MOSFET.
Adaptive Zero Shoot-Through Deadtime Control
These drivers incorporate an adaptive deadtime control
technique to minimize deadtime, resulting in high efficiency
from the reduced freewheeling time of the lower MOSFETs’
body-diode conduction, and to prevent the upper and lower
MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other
has turned off.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it drops below 1.75V, at which time the
UGATE is released to rise after 20ns of propagation delay.
Once the PHASE is high, the adaptive shoot-through
circuitry monitors the PHASE and UGATE voltages during a
PWM falling edge and the subsequent UGATE turn-off. If
either the UGATE falls to less than 1.75V above the PHASE
or the PHASE falls to less than +0.8V, the LGATE is
released to turn on.
Three-State PWM Input
A unique feature of these drivers and other Intersil drivers is
the addition of a shutdown window to the PWM input. If the
PWM signal enters and remains within the shutdown window
for a set holdoff time, the driver outputs are disabled and
both MOSFET gates are pulled and held low. The shutdown
state is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
This feature helps prevent a negative transient on the output
voltage when the output is shut down, eliminating the
Schottky diode that is used in some systems for protecting
the load from reversed output voltage events.
In addition, more than 400mV hysteresis also incorporates
into the three-state shutdown window to eliminate PWM
input oscillations due to the capacitive load seen by the
PWM
UGATE
LGATE
t
FL
t
PDHU
t
PDLL
t
RL
t
TSSHD
t
PDTS
t
PDTS
1.18V<PWM<2.36V
0.76V<PWM<1.96V
t
FU
t
RU
t
PDLU
t
PDHL
t
TSSHD
FIGURE 1. TIMING DIAGRAM
ISL6594A, ISL6594B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6594ACR | 功能描述:IC MOSFET DRVR SYNC BUCK 10-DFN RoHS:否 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動(dòng)器 - 外部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 配置:低端 輸入類型:非反相 延遲時(shí)間:40ns 電流 - 峰:9A 配置數(shù):1 輸出數(shù):1 高端電壓 - 最大（自引導(dǎo)啟動(dòng)）:- 電源電壓:4.5 V ~ 35 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:TO-263-6，D²Pak（5 引線+接片），TO-263BA 供應(yīng)商設(shè)備封裝:TO-263 包裝:管件 |
| ISL6594ACR-T | 功能描述:IC MOSFET DRVR SYNC BUCK 10-DFN RoHS:否 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動(dòng)器 - 外部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 配置:低端 輸入類型:非反相 延遲時(shí)間:40ns 電流 - 峰:9A 配置數(shù):1 輸出數(shù):1 高端電壓 - 最大（自引導(dǎo)啟動(dòng)）:- 電源電壓:4.5 V ~ 35 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:TO-263-6，D²Pak（5 引線+接片），TO-263BA 供應(yīng)商設(shè)備封裝:TO-263 包裝:管件 |
| ISL6594ACRZ | 功能描述:IC MOSFET DRVR SYNC BUCK 10-DFN RoHS:是 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動(dòng)器 - 外部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 配置:高端 輸入類型:非反相 延遲時(shí)間:200ns 電流 - 峰:250mA 配置數(shù):1 輸出數(shù):1 高端電壓 - 最大（自引導(dǎo)啟動(dòng)）:600V 電源電壓:12 V ~ 20 V 工作溫度:-40°C ~ 125°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-DIP 包裝:管件 其它名稱:*IR2127 |
| ISL6594ACRZ-T | 功能描述:IC MOSFET DRVR SYNC BUCK 10-DFN RoHS:是 類別:集成電路 (IC) >> PMIC - MOSFET，電橋驅(qū)動(dòng)器 - 外部開關(guān) 系列:- 標(biāo)準(zhǔn)包裝:6,000 系列:* |
| ISL6594ACRZ-TR5212 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
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