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參數(shù)資料
| 型號(hào)： | ISL6537CR-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | ACPI Regulator/Controller for Dual Channel DDR Memory Systems |
| 中文描述： | 3.3 A SWITCHING CONTROLLER, 280 kHz SWITCHING FREQ-MAX, PQCC28 |
| 封裝： | 6 X 6 MM, PLASTIC, MO-220-VJJC, QFN-28 |
| 文件頁(yè)數(shù)： | 14/15頁(yè) |
| 文件大?。?/td> | 560K |
| 代理商： | ISL6537CR-T |
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14
FN9142.4
February 8, 2005
turns on. Place the small ceramic capacitors physically close
to the MOSFETs and between the drain of upper MOSFET
and the source of lower MOSFET.
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current required by the regulator may be
closely approximated through the following equation:
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
MOSFET Selection - PWM Buck Converter
The ISL6537 requires 2 N-Channel power MOSFETs for
switching power and a third MOSFET to block backfeed from
V
DDQ
to the Input in S3 Mode. These should be selected
based upon r
DS(ON)
, gate supply requirements, and thermal
management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor. The switching losses seen when
sourcing current will be different from the switching losses
seen when sinking current. When sourcing current, the
upper MOSFET realizes most of the switching losses. The
lower switch realizes most of the switching losses when the
converter is sinking current (see the equations below).
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse-
recovery of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated in part by the ISL6537 and
do not significantly heat the MOSFETs. However, large gate-
charge increases the switching interval, t
SW
which increases
the MOSFET switching losses. Ensure that both MOSFETs
are within their maximum junction temperature at high
ambient temperature by calculating the temperature rise
according to package thermal-resistance specifications. A
separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
MOSFET Selection - LDO
The main criteria for selection of the linear regulator pass
transistor is package selection for efficient removal of heat.
Select a package and heatsink that maintains the junction
temperature below the rating with a maximum expected
ambient temperature.
The power dissipated in the linear regulator is:
where I
O
is the maximum output current and V
OUT
is the
nominal output voltage of the linear regulator.
I
RMSMAX
V
IN
-------------
I
OUTMAX
2
1
12
------
V
---------–
V
s
V
IN
-------------
×
2
×
+
×
=
P
LOWER
= Io
2
x r
DS(ON)
x (1 - D)
Where: D is the duty cycle = V
OUT
/ V
IN
,
t
SW
is the combined switch ON and OFF time, and
f
s
is the switching frequency.
Approximate Losses while Sourcing current
Io
2
r
DS ON
=
Approximate Losses while Sinking current
P
UPPER
= Io
2
x r
DS(ON)
x D
P
LOWER
Io
2
r
DS ON
)
×
1
D
–
(
)
×
1
2
--
Io
V
IN
×
t
SW
f
s
×
×
+
=
P
UPPER
)
×
D
×
1
2
--
Io
V
IN
×
t
SW
f
s
×
×
+
P
LINEAR
I
O
V
IN
V
OUT
–
(
)
×
ISL6537
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