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參數(shù)資料
| 型號： | ISL6537CRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 500-mA Peak Step-Up, Step-Down, Inverting Switching Voltage Regulator 14-SOIC 0 to 70 |
| 中文描述： | 3.3 A SWITCHING CONTROLLER, 280 kHz SWITCHING FREQ-MAX, PQCC28 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, PLASTIC, MO-220-VJJC, QFN-28 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 560K |
| 代理商： | ISL6537CRZ |
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6537
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6537 provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply V
DDQ
during S0/S1 and S3 states. During S0/S1
state, a fully integrated sink-source regulator generates an
accurate (V
DDQ
/2) high current V
TT
voltage without the
need for a negative supply. A buffered version of the V
DDQ
/2
reference is provided as V
REF
. Two LDO controllers are also
integrated for the GMCH core voltage regulation and for the
GMCH and CPU V
TT
termination voltage regulation.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±
2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU V
TT
termination voltage
is within spec and operational.
Each output is monitored for undervoltage events. The
switching regulator also has overvoltage and over current
protection. Thermal shutdown is integrated.
Pinout
ISL6537 (6x6 QFN)
TOP VIEW
Features
Generates 4 Regulated Voltages
- Synchronous Buck PWM Controller for DDR V
DDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR V
TT
- LDO Regulator for GMCH Core
- LDO Regulator for CPU/GMCH V
TT
Termination
ACPI compliant sleep state control
Glitch-free Transitions During State Changes
Integrated V
REF
Buffer
PWM Controller Drives Low Cost N-Channel MOSFETs
250kHz Constant Frequency Operation
Tight Output Voltage Regulation
- All Outputs:
±
2% Over Temperature
Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
Simple Single-Loop Voltage-Mode PWM Control Design
Fast PWM Converter Transient Response
Under and Over-voltage Monitoring on All Outputs
OCP on the Switching Regulator
Integrated Thermal Shutdown Protection
Pb-Free Available (RoHS Compliant)
Applications
Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
Graphics cards - GPU and memory supplies
ASIC power supplies
Embedded processor and I/O supplies
DSP supplies
1
2
3
4
5
6
7
21
20
19
18
17
16
15
28
27
26
25
24
23
22
8
9
10
11
12
13
14
DRIVE4
REFADJ4
DRIVE3
FB3
FB4
COMP
FB
5VSBY
S3#
P12V
GND
DDR_VTT
DDR_VTT
VDDQ
V
D
D
F
V
V
V
L
G
U
B
P
S
O
GND
29
Ordering Information
PART NUMBER
TEMP. RANGE
(°C)
PACKAGE
PKG.
DWG. #
ISL6537CR
0 to 70
28 Ld 6x6 QFN
L28.6x6
ISL6537CRZ
(See Note)
0 to 70
28 Ld 6x6 QFN
(Pb-free)
L28.6x6
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Data Sheet
February 8, 2005
FN9142.4
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