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參數(shù)資料
| 型號(hào)： | ISL6531CBZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination |
| 中文描述： | DUAL SWITCHING CONTROLLER, 325 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-013-AD, SOIC-24 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大小： | 461K |
| 代理商： | ISL6531CBZ |
7
While the V
TT
supply “floats”, it is held to about 50% of
V
DDQ
via a low current window regulator which drives V
TT
via the SENSE2 pin. The window regulator can overcome up
to at least
±
10mA of leakage on V
TT
.
While V2_SD is high, PGOOD is low.
PHASE1 and PHASE2
Connect PHASE1 and PHASE2 to the corresponding upper
MOSFET source. This pin is used as part of the upper
MOSFET bootstrapped drives. PHASE1 is used to monitor
the voltage drop across the upper MOSFET of the V
DDQ
regulator for overcurrent protection. The PHASE1 pin is
monitored by the adaptive shoot through protection circuitry
to determine when the upper FET of the V
DDQ
supply has
turned off.
FB1, COMP1
COMP1 and FB1 are the available external pins of the error
amplifier for the V
DDQ
regulator. The FB1 pin is the inverting
inputs of the error amplifier and the COMP1 pin is the
associated output. An appropriate AC network across these
pins is used to compensate the voltage-controlled feedback
loop of the V
DDQ
converter.
VREF and VREF_IN
VREF produces a voltage equal to one half of the voltage on
SENSE1. This low current output is connected to the VREF
input of the DDRAM devices being powered. This same
voltage is used as the reference input of the V
TT
error
amplifier. Thus V
TT
is controlled to 50% of V
DDQ
.
VREF_IN is used as an option to overdrive the internal
resistor divider network that sets the voltage for both
VREF_OUT and the reference voltage for the V
TT
supply. A
100pF capacitor between VREF_IN and ground is
recommended for proper operation.
PVCC1
This is the positive supply for the lower gate driver, LGATE1.
PVCC1 is connected to a well decoupled 5V.
SENSE1 and SENSE2
Both SENSE1 and SENSE2 are connected directly to the
regulated outputs of the V
DDQ
and V
TT
supplies,
respectively. SENSE1 is used as an input to create the
voltage at VREF_OUT and the reference voltage for the V
TT
supply. SENSE2 is used as the feedback pin of the V
TT
regulator and as the regulation point for the window regulator
that is enabled in V2_SD mode.
Functional Description
Overview
The ISL6531 contains control and drive circuitry for two
synchronous buck PWM voltage regulators. Both regulators
utilize 5V bootstrapped output topology to allow use of low
cost N-Channel MOSFETs. The regulators are driven by
300kHz clocks. The clocks are phase locked and displaced
90
o
to minimize noise coupling between the controllers.
The first regulator includes a precision 0.8V reference and is
intended to provide the proper V
DDQ
to a DDRAM memory
system. The V
DDQ
controller implements overcurrent
protection utilizing the r
DS(ON)
of the upper MOSFET.
Following a fault condition, the V
DDQ
regulator is softstarted
via a digital soft-start circuit.
Included in the ISL6531 is a precision V
REF
reference
output. V
REF
is a buffered representation of
is derived via a precision internal resistor divider connected
to the SENSE1 terminal.
. V
REF
The second PWM regulator is designed to provide V
TT
termination for the DDRAM signal lines. The reference to the
V
TT
regulator is V
REF
. Thus the V
TT
regulator provides a
termination voltage equal to
upper MOSFET of the V
TT
supply is connected to the
regulated V
DDQ
voltage. The V
TT
controller is designed to
enable both sinking and sourcing current on the V
TT
rail.
. The drain of the
Two benefits result from the ISL6531 dual controller
topology. First, as VREF is always
will track the V
DDQ
supply during soft-start cycles. Second,
the overcurrent protection incorporated into the V
DDQ
supply
will simultaneously protect the V
TT
supply.
, the V
TT
supply
Initialization
The ISL6531 automatically initializes upon application of
input power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltage at the VCC pin. The
POR function initiates soft-start operation after the 5V bias
supply voltage exceeds its POR threshold.
Soft-Start
The POR function initiates the digital soft start sequence. The
PWM error amplifier reference input for the VDDQ regulator is
clamped to a level proportional to the soft-start voltage. As the
soft-start voltage slews up, the PWM comparator generates
PHASE pulses of increasing width that charge the output
capacitor(s). This method provides a rapid and controlled
output voltage rise. The soft-start sequence typically takes
about 7ms.
With the V
TT
regulator reference held at
automatically track the ramp of the V
DDQ
softstart, thus
enabling a soft-start for V
TT
.
it will
Figure 2 shows the soft-start sequence for a typical application.
At T0, the +5V VCC bias voltage starts to ramp. Once the
voltage on VCC crosses the POR threshold at time T1, both
outputs begin their soft-start sequence. The triangle waveforms
from the PWM oscillators are compared to the rising error
amplifier output voltage. As the error amplifier voltage
increases, the pulse-widths on the UGATE pins increase to
reach their steady-state duty cycle at time t2.
1
2
--
V
DDQ
1
2
--
V
DDQ
1
2
--
V
DDQ
1
2
--
V
DDQ
ISL6531
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