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參數(shù)資料
| 型號(hào)： | ISL6531CBZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination |
| 中文描述： | DUAL SWITCHING CONTROLLER, 325 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-013-AD, SOIC-24 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 461K |
| 代理商： | ISL6531CBZ |
14
current (see the equations below). These equations assume
linear voltage-current transitions and do not adequately model
power loss due the reverse-recovery of the upper and lower
MOSFET’s body diode. The gate-charge losses are dissipated
by the ISL6531 and don't heat the MOSFETs. However, large
gate-charge increases the switching interval, t
SW
which
increases the
MOSFET
switching losses.
Ensure that both MOSFETs are within their maximum junction
temperature at high ambient temperature by calculating the
temperature rise according to package thermal-resistance
specifications. A separate heat sink may be necessary
depending upon MOSFET power, package type, ambient
temperature and air flow.
Given the reduced available gate bias voltage (5V), logic-
level or sub-logic-level transistors should be used for both N-
MOSFETs. Caution should be exercised when using devices
with very low gate thresholds (V
TH
). The shoot-through
protection circuitry may be circumvented by these
MOSFETs. Very high dv/dt transitions on the phase node
may cause the Miller capacitance to couple the lower gate
with the phase node and cause an undesireable turn on of
the lower MOSFET while the upper MOSFET is on.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 10. The
boot capacitor, C
BOOT
, develops a floating supply voltage
referenced to the PHASE pin. This supply is refreshed each
cycle, when D
BOOT
conducts, to a voltage of VCC less the
boot diode drop, V
D
, plus the voltage rise across Q
LOWER
.
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
upper MOSFET as shown:
where Q
GATE
is the maximum total gate charge of the upper
MOSFET, C
BOOT
is the bootstrap capacitance, V
BOOT1
is
the bootstrap voltage immediately before turn-on, and
V
BOOT2
is the bootstrap voltage immediately after turn-on.
The bootstrap capacitor begins its refresh cycle when the
gate drive begins to turn-off the upper MOSFET. A refresh
cycle ends when the upper MOSFET is turned on again,
which varies depending on the switching frequency and
duty cycle.
The minimum bootstrap capacitance can be calculated by
rearranging the previous equation and solving for CBOOT.
Typical gate charge values for MOSFETs considered in
these types of applications range from 20 to 100nC. Since
the voltage drop across Q
LOWER
is negligible, V
BOOT1
is
simply VCC - V
D
. A schottky diode is recommended to
minimize the voltage drop across the bootstrap capacitor
during the on-time of the upper MOSFET. Initial calculations
with V
BOOT2
no less than 4V will quickly help narrow the
bootstrap capacitor range.
For example, consider an upper MOSFET is chosen with a
maximum gate charge, Q
g
, of 100nC. Limiting the voltage
drop across the bootstrap capacitor to 1V results in a value
of no less than 0.1
μ
F. The tolerance of the ceramic capacitor
should also be considered when selecting the final bootstrap
capacitance value.
A fast recovery diode is recommended when selecting a
bootstrap diode to reduce the impact of reverse recovery
charge loss. Otherwise, the recovery charge, Q
RR
, would
have to be added to the gate charge of the MOSFET and
taken into consideration when calculating the minimum
bootstrap capacitance.
P
LOWER
= Io
2
x r
DS(ON)
x (1 - D)
Where: D is the duty cycle = V
OUT
/ V
IN
,
t
SW
is the combined switch ON and OFF time, and
f
s
is the switching frequency.
LOSSES WHILE SOURCING CURRENT
Io
2
r
DS ON
LOSSES WHILE SINKING CURRENT
P
UPPER
= Io
2
x r
DS(ON)
x D
P
LOWER
Io
2
r
DS ON
)
×
1
D
–
(
)
×
1
2
--
Io
V
IN
×
t
SW
f
s
×
×
+
=
P
UPPER
)
×
D
×
1
2
--
Io
V
IN
×
t
SW
f
s
×
×
+
=
Q
GATE
C
BOOT
V
BOOT1
V
BOOT2
–
(
)
×
=
ISL6531
GND
LGATEn
UGATEn
PHASEn
BOOTn
V
IN
NOTE:
V
G-S
≈
V
CC
-V
D
NOTE:
V
G-S
≈
V
CC
C
BOOT
D
BOOT
Q
UPPER
Q
LOWER
+
FIGURE 10. UPPER GATE DRIVE BOOTSTRAP
+
V
D
-
VCC
C
BOOT
Q
–
V
BOOT1
V
BOOT2
----------------------------------------------------
≥
ISL6531
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