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參數(shù)資料
| 型號： | ISL6529A |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller |
| 中文描述： | 雙Regulator.Synchronous整流降壓PWM和線性功率控制器 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 376K |
| 代理商： | ISL6529A |
10
FN9127.1
December 28, 2004
controllable closed loop transfer function of V
OUT
/V
REF
. The
goal of component selection for the compensation network is
to provide a loop gain with high 0dB crossing frequency
(f
0dB
) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f
0dB
and 180
degrees.
Compensation Break Frequency Equations
Poles:
Follow this procedure for selecting compensation
components by locating the poles and zeros of the
compensation network:
1. Set the loop gain (R2/R1) to provide a converter
bandwidth of one quarter of the switching frequency.
2. Place the first
compensation zero, F
Z1
, below the output
filter double pole (~75% F
LC
).
3. Position the second compensation zero, F
Z2
, at the
output filter double pole, F
LC
.
4. Locate the first compensation pole, F
P1
, at the output
filter ESR zero, F
ESR
.
5. Position the second compensation pole at half the
converter switching frequency, F
SW
.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
Figure
7
shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure
7
. Using the above
procedure should yield a compensation gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
P2
with the capabilities of the error amplifier.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Linear Regulator Feedback Compensation
The regulator may be compensated with a series 6.8k
resistor and a 470pF capacitor connected between FB2 and
DRIVE2. This will provide compensation for all loads and
ranges of output capacitor values and a range of capacitor
ESR values from aluminum electrolytic to low-ESR organic
polymer capacitors. This will not insure optimum load
transient response since the regulator system, like an
internally compensated operational amplifier is
overcompensated.
To optimize transient response, when required, the regulator
should be in the actual application circuit with the desired
output capacitors and associated PC board parasitics and
load. The value of C4 would be reduced and the series
resistor, R12 adjusted for optimum rise and fall time, with a
minimum of overshoot.
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
600kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit board design minimizes the voltage
spikes in the converters.
As an example, consider the turn-off transition of the PWM
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET and
parasitic diode. Any parasitic inductance in the switched
current path generates a large voltage spike during the
switching interval. Careful component selection, tight layout
of the critical components, and short, wide traces minimizes
the magnitude of voltage spikes.
There are two sets of critical components in a DC-DC converter
using the ISL6529A. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are the
small signal components which connect to sensitive nodes or
supply critical bypass current and signal coupling.
F
Z1
π
R
×
2
C1
×
2
=
F
Z2
+
π
R1
R3
(
)
C3
×
×
2
=
F
P1
2
π
R
2
C2
C2
×
+
C1
×
×
-------------------------1
=
F
P2
π
R
×
3
C3
×
2
=
(EQ. 10)
(EQ. 11)
(EQ. 8)
(EQ. 9)
Zeros:
FIGURE 7. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
F
LC
F
ESR
COMPENSATION
GAIN
G
FREQUENCY (Hz)
MODULATOR
GAIN
LOOP GAIN
20
VOSC
log
20
--------
log
ISL6529A
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