- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383147 > ISL6424 (Intersil Corporation) Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs PDF資料下載
參數(shù)資料
| 型號(hào)： | ISL6424 |
| 廠商： | Intersil Corporation |
| 英文描述： | Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs |
| 中文描述： | 雙輸出LNB電源和控制穩(wěn)壓器，帶有I2C接口的先進(jìn)衛(wèi)星機(jī)頂盒設(shè)計(jì) |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 374K |
| 代理商： | ISL6424 |
9
FN9175.3
September 13, 2005
in the standard-mode or up to 400Kbps in the fast-mode. The
level of logic “0” and logic “1” is dependent of associated value
of V
DD
as per electrical specification table. One clock pulse is
generated for each data bit transferred.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 2.
START and STOP Conditions
As shown in Figure 3, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 4).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6424 will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
decreases the noise immunity.
ISL6424 Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
A start condition (S)
A chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I
2
C slave
address for the ISL6424 is 0001 00XX)
A sequence of data (1 byte + Acknowledge)
A stop condition (P)
SDA
SCL
DATA LINE
STABLE
DATA VALID
CHANGE
OF DATA
ALLOWED
FIGURE 2. DATA VALIDITY
SDA
SCL
START
CONDITION
FIGURE 3. START AND STOP WAVEFORMS
STOP
CONDITION
S
P
TABLE 2. INTERFACE PROTOCOL
S
0
0
0
1
0
0
0
R/W ACK
Data (8 bits)
ACK P
SDA
SCL
FIGURE 4. ACKNOWLEDGE ON THE I
2
C BUS
1
2
8
9
ACKNOWLEDGE
FROM SLAVE
MSB
START
ISL6424
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISL6424ER-T | Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs |
| ISL6424ERZ | Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs |
| ISL6424ER | Quadruple 2-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| ISL6424ERZ-T | Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs |
| ISL6425ERZ-T | Single Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6424ER | 功能描述:IC REG DUAL LNBP TTL-INP 32-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,000 系列:- 應(yīng)用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應(yīng)商設(shè)備封裝:42-WLP 包裝:帶卷 (TR) |
| ISL6424ER-T | 功能描述:IC REG DUAL LNBP TTL-INP 32-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,000 系列:- 應(yīng)用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應(yīng)商設(shè)備封裝:42-WLP 包裝:帶卷 (TR) |
| ISL6424ERZ | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 DL LNBP SUPP CONTROL VG W/TTL INPUTS 3 RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| ISL6424ERZ-T | 功能描述:直流/直流開關(guān)調(diào)節(jié)器 DL LNBP SUPP CONTROL VG W/TTL INPUTS 3 RoHS:否 制造商:International Rectifier 最大輸入電壓:21 V 開關(guān)頻率:1.5 MHz 輸出電壓:0.5 V to 0.86 V 輸出電流:4 A 輸出端數(shù)量: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFN 4 x 5 |
| ISL6425ER | 功能描述:IC REG DUAL LNBP TTL-INP 32-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,000 系列:- 應(yīng)用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應(yīng)商設(shè)備封裝:42-WLP 包裝:帶卷 (TR) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。