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參數(shù)資料
| 型號： | ISL6424 |
| 廠商： | Intersil Corporation |
| 英文描述： | Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs |
| 中文描述： | 雙輸出LNB電源和控制穩(wěn)壓器，帶有I2C接口的先進衛(wèi)星機頂盒設(shè)計 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 374K |
| 代理商： | ISL6424 |
8
FN9175.3
September 13, 2005
When the ENT1/2 bit is set HIGH, a continuous 22kHz tone
is generated regardless of the DSQIN1/2 pin logic status for
the corresponding regulator channel (LNB-A or LNB-B). The
ENT1/2 bit must be set LOW when the DSQIN1 and/or
DSQIN2 pin is used for DiSEqC encoding.
Linear Regulator
The output linear regulator will sink and source current. This
feature allows full modulation capability into capacitive loads
as high as 0.25
μ
F. In order to minimize the power
dissipation, the output voltage of the internal step-up
converter is adjusted to allow the linear regulator to work at
minimum dropout.
When the device is put in the shutdown mode (EN1,
EN2 = LOW), both PWM power blocks are disabled. (i.e.
when EN1 = 0, PWM1 is disabled, and when EN2 = 0,
PWM2 is disabled).
When the regulator blocks are active (EN1, EN2 = HIGH),
the output can be logic controlled to be 13V or 18V (typical)
by means of the VSEL bit (Voltage Select) for remote
controlling of non-DiSEqC LNBs. Additionally, it is possible
to increment by 1V (typical) the selected voltage value to
compensate for the excess voltage drop along the coaxial
cable (LLC1/2 bit HIGH).
Output Timing
The programmed output voltage rise and fall times can be
set by an external capacitor. The output rise and fall times
will be approximately 3400 times the TCAP value. For the
recommended range of 0.47
μ
F to 2.2
μ
F, the rise and fall
time would be 1.6ms to 7.6ms. Using a 0.47
μ
F capacitor
insures the PWM stays below its overcurrent threshold when
charging a 120
μ
F VSW filter cap during the worst case 13V
to 19V transition. A typical value of 1.0
μ
F is recommended.
This feature only affects the turn-on and programmed
voltage rise and fall times.
Current Limiting
The current limiting block has two thresholds that can be
selected by the ISEL bit of the SR and can work either
statically (simple current clamp) or dynamically. The lower
threshold is between 425mA and 550mA (ISEL = L), while
the higher threshold is between 775mA and 950mA
(ISEL = H). When the DCL (Dynamic Current Limiting) bit is
set to LOW, the overcurrent protection circuit works
dynamically: as soon as an overload is detected, the output
is shutdown for a time t
OFF
, typically 900ms. Simultaneously
the OLF bit of the System Register is set to HIGH. After this
time has elapsed, the output is resumed for a time t
ON
=
20ms. During t
ON
, the device output will be current limited to
425mA min. or 775mA min., depending on the ISEL bits. At
the end of t
ON
, if the overload is still detected, the protection
circuit will cycle again through t
OFF
and t
ON
. At the end of a
full t
ON
in which no overload is detected, normal operation is
resumed and the OLF bit is reset to LOW. Typical t
ON
+ t
OFF
time is 920ms as determined by an internal timer. This
dynamic operation can greatly reduce the power dissipation
in a short circuit condition, still ensuring excellent power-on
start-up in most conditions.
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up
when the dynamic protection is chosen. This can be solved
by initiating any power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a chosen amount of time. When in static mode, the OLF1/2
bit goes HIGH when the current limit threshold at the CS pin
reaches 0.45V typ and returns LOW when the overload
condition is cleared. The OLF1/2 bit will be LOW at the end of
initial power-on soft-start.
Thermal Protection
This IC is protected against overheating. When the junction
temperature exceeds 150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the
SR is set HIGH. Normal operation is resumed and the OTF
bit is reset LOW when the junction is cooled down to 135°C
(typical).
In over temperature conditions, the OTF Flag goes HIGH
and the I
2
C data will be cleared. The user may need to
monitor the I
2
C enable bits and OTF flag continuously and
enable the chip, if I
2
C data is cleared. OTF conditions may
also make the OLF flags go HIGH, when high capacitive
loads are present or self-heating conditions occur at higher
loads.
External Output Voltage Selection
The output voltage can be selected by the I
2
C bus.
Additionally, the package offers two pins (SEL18V1,
SEL18V2) for independent 13V/18V output voltage
selection. When using these pins, the I
2
C bits should be
initialized to 13V status.
I
2
C Bus Interface for ISL6424
(Refer to Philips I
2
C Specification, Rev. 2.1)
Data transmission from main microprocessor to the ISL6424
and vice versa takes place through the two wire I
2
C bus
interface, consisting of the two lines SDA and SCL. Both SDA
and SCL are bidirectional lines, connected to a positive supply
voltage via a pull up resistor. (Pull up resistors to positive supply
voltage must be externally connected). When the bus is free,
both lines are HIGH. The output stages of ISL6424 will have an
open drain/open collector in order to perform the wired-AND
function. Data on the I
2
C bus can be transferred up to 100Kbps
TABLE 1.
I
2
C BITS
SEL18V (1, 2)
O/P VOLTAGE
13V
Low
13V
14V
Low
14V
13V
High
18V
14V
High
18V
ISL6424
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