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參數(shù)資料
| 型號： | ISL6424 |
| 廠商： | Intersil Corporation |
| 英文描述： | Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs |
| 中文描述： | 雙輸出LNB電源和控制穩(wěn)壓器，帶有I2C接口的先進(jìn)衛(wèi)星機(jī)頂盒設(shè)計 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 374K |
| 代理商： | ISL6424 |
11
FN9175.3
September 13, 2005
Received Data (
I
2
C
bus READ MODE)
The ISL6424 can provide to the master a copy of the system
register information via the I
2
C bus in read mode. The read
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6424 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6424.
Not acknowledge, stopping the read mode
communication.
While the whole register is read back by the microprocessor,
the read-only bits OLF1, OLF2, and OTF convey diagnostic
information about the ISL6424.
Power-On I
2
C Interface Reset
The I
2
C interface built into the ISL6424 is automatically reset
at power-on. The I
2
C interface block will receive a Power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I
2
C commands and the
system register SR1 and SR2 are initialized to all zeros, thus
keeping the power blocks disabled. Once the Vcc rises
above UVLO, the POWER OK signal given to the I
2
C
interface block will be HIGH, the I
2
C interface becomes
operative and the SRs can be configured by the main
microprocessor. About 400mV of hysteresis is provided in
the UVLO threshold to avoid false triggering of the Power-
On reset circuit. (I
2
C comes up with EN = 0; EN goes HIGH
at the same time as (or later than) all other I
2
C data for that
PWM becomes valid).
ADDRESS Pin
Connecting this pin to GND the chip I
2
C interface address is
0001000, but, it is possible to choose between two different
addresses simply by setting this pin at one of the two fixed
voltage levels as shown in Table 8.
I
2
C Electrical Characteristics
TABLE 6. ADDRESS PIN CHARACTERISTICS
V
ADDR
MINIMUM
TYPICAL
MAXIMUM
V
ADDR
-1
“0001000”
0V
-
2V
V
ADDR
-2
“0001001”
2.7V
-
5V
TABLE 7. READING SYSTEM REGISTERS
DCL
ISEL1/2
ENT1/2
LLC1/2
VSEL1/1
EN1/2
OTF2
OLF1/2
FUNCTION
These bits are read as they were after the last write operation.
0
T
J
≤
130°C, normal operation
1
T
J
> 150°C, power blocks disabled
0
I
OUT
< I
MAX
, normal operation
1
I
OUT
> I
MAX
, overload protection triggered
TABLE 8. I
2
C SPECIFICATIONS
PARAMETER
TEST CONDITION
MINIMUM
TYPICAL
MAXIMUM
Input Logic High, VIH
SDA, SCL
0.7 x V
DD
Input Logic Low, VIL
SDA, SCL
0.3 x V
DD
Input Logic Current, IIL
SDA, SCL;
0.4V < V
IN
< 4.5V
10
μ
A
SCL Clock Frequency
0
100kHz
400kHz
ISL6424
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