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參數(shù)資料
| 型號(hào)： | ISL55100BIRZ-T |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP DRVR/WINDOW 18V 72-QFN |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | LVDS |
| 電源電壓： | 15 V ~ 18 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN-EP（10x10） |
| 包裝： | 帶卷 (TR) |
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3
FN6229.1
November 24, 2008
Pin Descriptions
PIN
FUNCTION
DATA+(0:3)
Positive differential digital input that determines the driver output state when it is enabled.
DATA-(0:3)
Negative differential digital input that determines the driver output state when it is enabled.
DRV EN+(0:3) Positive differential digital input that enables or disables the corresponding driver.
DRV EN-(0:3)
Negative differential digital input that enables or disables the corresponding driver.
QA (0:3)
Comparator digital outputs. QA(X) is high when VINP(X) exceeds CVA(X).
QB (0:3)
Comparator digital outputs. QB(X) is high when VINP(X) exceeds CVB(X).
DOUT (0:3)
Driver outputs.
VINP (0:3)
Comparator inputs.
VH (0:3)
Unbuffered analog inputs that set each individual driver’s “high” voltage level.
VL (0:3)
Unbuffered analog inputs that set each individual driver’s “l(fā)ow” voltage level. VL must be a lower voltage than VH.
NC
No internal connection.
CVA (0:3)
Analog inputs that set the threshold for the corresponding Channel A comparators.
CVB (0:3)
Analog inputs that set the threshold for the corresponding Channel B comparators.
COMP HI
Supply voltage, unbuffered input that sets the high output level of all comparators. Must be greater than COMP LO.
COMP LO
Supply voltage, unbuffered input that sets the low output level of all comparators. Must be less than COMP HI.
VCC
Positive power supply (5% tolerance).
VEE
Negative power supply (5% tolerance).
VEXT
External 5.5VDC power supply (5.5VDC to 6.0VDC as referenced to VEE, NOT GND. Recommended VEXT = 5.5V) for internal
logic. Connect pin to VEE when not using an external supply.
LOWSWING
Input that selects driver output configurations optimized to yield minimum overshoots for low level swings (VH < VEE +5V), or
optimized for large output swings. Connect LOWSWING to VEE to select low swing circuitry, or connect it to VCC to select high
swing circuitry.
Truth Tables
DRIVERS
INPUTS
OUTPUT
DATA
DRV EN
DOUT
X+ > -
Hi - Z
+ > -
+ < -
VH
+ < -
VL
X = DON’T CARE
RECEIVERS
INPUT
OUTPUTS
VINP
QA
QB
<CVA
<CVB
0
<CVA
>CVB
0
1
>CVA
<CVB
1
0
>CVA
>CVB
1
ISL55100B
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