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參數(shù)資料
| 型號： | ISL5416KI |
| 廠商： | INTERSIL CORP |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | Four-Channel Wideband Programmable DownConverter |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 40/71頁 |
| 文件大?。?/td> | 2013K |
| 代理商： | ISL5416KI |
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40
TABLE 31. SERIAL OUTPUT CONTROL (IWA = 0*06h)
RESET STATE = 0x00000000h
P(31:0)
FUNCTION
31:30
RESERVED. Set to 0.
29
SCLK ENABLE.
1 = enable
The serial clock generator is shared by the four serial outputs. A serial clock pin is provided for each output. Each pin can be enabled
or disabled independent of the other channels.
28
SSYNCX POLARITY.
1 = Active Low.
0 = Active High.
The SSYNCX signal is asserted for one serial clock period for each time slot where SSYNC is enabled.
27:26
RESERVED. Set to 0.
25:24
SSYNCX POSITION.
00 = Early SSYNC. SSYNCX is asserted during the serial clock period prior to the first data bit for each slot where SSYNC is enabled.
01 = Late SSYNC. SSYNCX is asserted during the serial clock period following the last data bit for each slot where SSYNC is enabled.
1X = Coincident SSYNC. SSYNCX is asserted during the serial clock period of first data bit for each slot where SSYNC is enabled.
23:20
RESERVED. Set to 0.
19:16
SD1X ROUTING MASK.
These bits gate the serial output of each channel to any or all 4 serial output pins. The gated serial outputs from all of the channels
are ORed together. This allows channels to be multiplexed together on a single serial output by offsetting the serial data streams from
each other using the hold off delay below or by using empty time slots. Note that the serial data from each channel is zeroed after all
of the slots have been output, so it will not interfere with a delayed channel. The multiplexing of the SSYNCX signals matches the
data multiplexing.
19 - Enable the serial output to the SD1D pin.
18 - Enable the serial output to the SD1C pin.
17 - Enable the serial output to the SD1B pin.
16 - Enable the serial output to the SD1A pin.
15:12
SD2X ROUTING MASK.
15 - Enable the serial output to the SD2D pin.
14 - Enable the serial output to the SD2C pin.
13 - Enable the serial output to the SD2B pin.
12 - Enable the serial output to the SD2A pin.
11:0
OUTPUT HOLD OFF DELAY.
These bits control a programmable hold off delay from the time a set of data samples is provided to the serial output section to the
time that the serial output begins. The delay is programmed in serial clocks. Program with the desired number of serial clocks:
0 = no delay
TABLE 32. SERIAL OUTPUT SD1X SLOT CONTROL (IWA = 0*07h)
RESET STATE = 0x00000000h
P(31:0)
FUNCTION
31
SLOT 4 SYNC ENABLE.
1 = SSYNCX active for this time slot
0 = no SSYNCX for this time slot
30:27
SLOT 4 WORD WIDTH.
0000 = 0-bit*
0001 = 4-bit
0010 = 6-bit
0011 = 8-bit
0100 = 10-bit
0101 = 12-bit
0110 = 16-bit
0111 = 20-bit
1000 = 24-bit
1001 = 32-bit (8 LSBs zeroed)
All other codes are invalid. Note that if the channel output is rounded to fewer than 24 bits and fewer than 24 bits is selected for the
slot width, the output will be doubly rounded.
* if 0-bit is selected for slot 1, 2, or 3, one SCLK period will actually be used, though no data will be output.
ISL5416
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