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參數(shù)資料
| 型號： | ISL45042IR-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 0K |
| 描述： | IC LCD MODULE CALIBRATOR 8-DFN |
| 標準包裝： | 6,000 |
| 類型： | 校準器 |
| 應用： | LCD 顯示器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應商設備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
7
FN6072.9
April 13, 2011
Power Supply Sequence
The recommended power supply sequencing is shown in
Figure 6. When applying power, VDD should be applied
before or at the same time as AVDD. The minimum time for
tVS is 0s. When removing power, the sequence of VDD and
AVDD is not important. Do not remove VDD or AVDD within
100ms of the start of the EEPROM programming cycle.
Removing power before the EEPROM programming cycle is
completed may result in corrupted data in the EEPROM.
Verifying the Programmed Value
The following sequence can be used to verify the
programmed value without having to sequence the VDD
supply. To verify the programmed value, follow the following
steps. The ISL45042 will read memory contents and be set
to that value when the CE pin is grounded.
1. Power-up the ISL45042.
2. CE pin = VDD.
3. Change counter value with CTL pin to desired value.
4. CTL = more than 4.9V and 200ms. Counter value
programmed.
5. Change the counter value with CTL pin to a different
value.
6. CE pin = Ground.
7. Check that the output value is the one programmed in
Step 4.
Generating VDD and CE supply from a Larger
Voltage Source
The CE pin has an internal pull-down resistor (see
400k
Ω to 5MΩ. If your design is using a resistor divider
network to generate the 3.3V supply (for both VDD and CE to
enable programming) from a larger voltage source, the
400k
Ω (worst case) resistor needs to be taken into account
as a parallel resistance when the CE pin is connected to this
source. Another design concern is to be able to provide
enough supply current during programming. The ISL45042
draws about 2mA during this process. Recommended
resistor values are shown in Figure 7. This design will result
in an additional 0.83mA quiescent current flowing through
resistors RA and RB.
FIGURE 6. POWER SUPPLY SEQUENCE
VDD
AVDD
tVS
FIGURE 7. APPLICATION GENERATING VDD AND VCE
VOLTAGES
VCC = 5V
SCHMITT
TRIGGER
CE LOGIC
RINTERNAL = 400kΩ to 5MΩ
RA
RB
2k
Ω
4k
Ω
ISL45042
CE
VCE
ISL45042
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