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參數(shù)資料
| 型號： | ISL45042IR-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LCD MODULE CALIBRATOR 8-DFN |
| 標準包裝： | 6,000 |
| 類型： | 校準器 |
| 應用： | LCD 顯示器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應商設備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
4
FN6072.9
April 13, 2011
CTL EEPROM Program Voltage
CTLPROM
Full
4.9
-
15.75
V
CTL EEPROM Programming
Signal Time
CTLPT
>4.9V
Full
200
-
s
Programming Time
PT
Full
-
100
ms
SET Voltage Resolution
SETVR
(Note 8)
Full
7
Bits
SET Differential Nonlinearity
SETDN
Monotonic Over-Temperature
Full
-
±1
LSB
SET Zero-Scale Error
SETZSE
Full
-
±3
LSB
SET Full-Scale Error
SETFSE
Full
-
±8
LSB
SET Current
ISET
Full
-
20
-
A
SET External Resistance
SETER
To GND, AVDD = 20V
Full
10
-
200
k
Ω
To GND, AVDD = 4.5V
Full
2.25
-
45
k
Ω
To GND, AVDD = 15V, VDD = 3V
Full
1
-
200
k
Ω
AVDD to SET Voltage Attenuation
AVDD to SET
Full
-
1:20
-
V/V
OUT Settling Time
OUTST
To ±0.5 LSB Error Band (Note 9)
Full
-
20
-
s
OUT Voltage Range
VOUT
Full
VSET + 0.5V
-
13
V
OUT Voltage Drift
OUTVD
25 to 55
-
<10
-
mV
NOTES:
6. CTL signal only needs to be greater than 4.9V to program EEPROM.
7. Tested at AVDD = 20V.
8. The Counter value is set to mid-scale ±4 LSB’s in the Production.
9. Simulated and Determined via Design and NOT Directly Tested.
10. Simulated Maximum Current Draw when Programming EEPROM is 23mA; should be considered when designing Power Supply.
11. A Typical Current of 20A is Calculated using AVDD = 10V and RSET = 24.9kΩ. Reference “RSET Resistor” on page 6.
12. Minimum value of RSET resistor guaranteed when: AVDD = 15V, VDD = 3.0V and when voltage on the VOUT pin is greater than 2.5V. Reference
13. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications
Test Conditions: VDD = 3V, AVDD = 18V, RSET = 5k, R1 = 10k, R2 = 10k; Unless Otherwise Specified.
Typicals are at TA = +25°C (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 13)
TYP
MAX
(Note 13) UNITS
ISL45042
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