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參數(shù)資料
| 型號： | ISL45042IR-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LCD MODULE CALIBRATOR 8-DFN |
| 標(biāo)準(zhǔn)包裝： | 6,000 |
| 類型： | 校準(zhǔn)器 |
| 應(yīng)用： | LCD 顯示器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
5
FN6072.9
April 13, 2011
Application Information
The application circuit to adjust the VCOM voltage in an LCD
panel is shown in Figure 1. The ISL45042 has a 128-step
sink current resolution. The output is connected to an
external voltage divider that decreases the output VCOM
voltage as you increase the ISL45042 sink current.
CTL Pin
The adjustment of the output VCOM voltage and the
programming of the non-volatile memory are provided
through a single pin called CTL when the CE pin is high.
The output VCOM voltage is increased with a mid (VDD/2) to
high transition (0.8*VDD) on the CTL pin. The output VCOM
voltage is decreased with a mid (VDD/2) to low transition
or maximum value is reached on the 128 steps, the device
will not overflow or underflow beyond that minimum or
maximum value.
Programming of the non-volatile memory occurs when the
CTL pin exceeds 4.9V. The CTL signal needs to remain
above 4.9V for more than 200s. The level and timing
needed to program the non-volatile memory is given in
Figure 2. It then takes a maximum of 100ms for the
programming to be completed inside the device.
When the part is programmed, the counter setting is loaded
into the non-volatile memory. This value will be loaded from
the non-volatile memory during initial power-up or when the
CE pin is pulled low.
Once the programming is completed, it is recommended that
the user float the CTL pin. The CTL pin is internally tied to a
resistor network connected to ground. If left floating, the
voltage at the CTL pin will equal VDD/2. Under these
conditions, no additional pulses will be seen by the Up/Down
counter via the CTL pin. To prevent further programming,
ground the CE pin.
CTL should have a noise filter to reduce bouncing or noise
on the input that could cause unwanted counting when the
CE pin is high. The board should have an additional ESD
protection circuit, with a series 1k
Ω resistor and a shunt
0.01F capacitor connected on the CTL pin, (see Figure 3).
To avoid unintentional adjustment, the ISL45042 guarantees
to reject CTL pulses shorter than 20s.
During Initial Power-up (only), to avoid the possibility of a
false pulse (since the internal comparators come up in an
unknown state), the very first CTL pulse is ignored. See
Figure 8 for the timing information.
CE Pin
To adjust the output voltage, the CE pin must be pulled high
(VDD). The CE pin has an internal pull-down resistor to
prevent unwanted reprogramming of the EEPROM. To
minimize current consumption, the impedance of this resistor
is high: 400k
Transitions of the CE pin are recommended to be less than
10s.
Replacing Existing Mechanical Potentiometer
Circuits
Figure 4 shows the common adjustment mechanical circuits
and equivalent replacement with the ISL45042.
RSET
FIGURE 1. VCOM ADJUSTMENT IN AN LCD PANEL
ISL45042
SET
OUT
AVDD
R1
R2
AVDD
ISINK
VCOM
SINGLE PIXEL
CTL
CE
IN LCD PANEL
RED
G
R
EEN
BL
UE
+
-
COLUMN
DRIVER
CTL VOLTAGE
TIME
4.9V
CTLPT
FIGURE 2. EEPROM PROGRAMMING
>200s
ISL45042
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