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參數(shù)資料
| 型號： | ISL2671286IBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SPI/SRL 20K 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 980 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 20k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
ISL2671286
12
FN7863.0
November 1, 2011
activated. After reset is complete, a single dummy cycle lasting
one conversion must be executed to initialize the switched
capacitor track and hold. Once the dummy cycle is complete, the
ADC mode is determined by the state of CS/SHDN. At this point,
switching between dynamic and static modes is controlled by
CS/SHDN, with no delay required between states.
POWER vs THROUGHPUT RATE
The ISL2671286 power consumption is reduced slightly at lower
conversion rates. Figure 29 shows the typical power consumption
over a wide range of throughput rates.
Serial Digital Interface
The ISL2671286 communicates using a 3-wire serial interface.
DCLOCK synchronizes the data transfer, with each bit
transmitted on the falling DCLOCK edge and captured on the
rising DCLOCK edge in the receiving system. A falling CS/SHDN
initiates data transfer, as shown in Figure 3. After CS/SHDN falls,
the second DCLOCK pulse enables DOUT. After one null bit, the
A/D conversion result is output on the DOUT line. Bringing
CS/SHDN high resets the ISL2671286 for the next data
exchange.
Figure 3 shows a detailed timing diagram for the serial interface.
The serial clock provides the conversion clock and controls the
transfer of data during conversion. CS/SHDN initiates the
conversion process and frames the data transfer. The falling
edge of CS/SHDN puts the track-and-hold into hold mode and
takes the bus out of three-state. The analog input is sampled and
the conversion initiated at this point.
The conversion result from the ISL2671286 is provided on DOUT
output as a serial data stream. The bits are clocked out on the
falling of the SCLK input. The output coding is two’s complement.
Applications Information
Analog Input Filtering
A low-pass, anti-alias filter is recommended to optimize
performance, as shown in Figure 31. The capacitive input
switching currents are averaged into a net DC current by CFILT. It
is recommended that a high-quality capacitor with low voltage
and temperature coefficients, such as C0G/NP0, be used. A
small series resistance value minimizes voltage drops across the
resistor.
Reduced Reference Operation
The ISL2671286 exhibits good linearity and gain over a wide
operating at low values of VREF, offset errors and noise must be
considered because of the reduced LSB size.
Input errors can have a larger impact on performance when
operating the ADC with a reduced reference voltage, since LSB
size is proportional to VREF. Figure 8 shows how the offset in
LSBs is related to reference voltage for a typical value of VOS. For
example, a VOS of 100V is 0.082 LSB with a 5V reference. If
VREF is reduced to 1V, the same 100V offset is 0.41 LSB, and it
increases to 2.05 LSB with a 0.2V reference. The offset can be
corrected digitally after conversion, or an opposing bias can be
applied to the –IN pin (within the allowable range according to
Similarly, total input referred noise appears as a larger fraction of
an LSB when operating at reduced VREF values. Attention should
be paid to the output noise of the driving amplifier, and proper
filtering should be applied to limit the noise that aliases in the
Nyquist zone. Averaging multiple readings can improve
performance if the application conditions allow.
Grounding and Layout
The printed circuit board that houses the ISL2671286 should be
designed so that the analog and digital sections are separated
FIGURE 29. SUPPLY CURRENT vs SAMPLE RATE
1
10
100
1000
0.1
1.0
10
100
SAMPLE RATE (kHz)
SUP
P
LY
CUR
RE
NT
(A)
TA = 25°C
VCC = +5V
VREF = +5V
fCLK = 16 x fSAMPLE
FIGURE 30. SHUTDOWN CURRENT vs SAMPLE RATE
0
1
2
3
4
5
6
0.1
1.0
10
100
SAMPLE RATE (kHz)
TA = 25°C
VCC = +5V
VREF = +5V
fCLK = 16 x fSAMPLE
CSB = LOW
(GND)
CSB = HIGH
(VCC)
SUPP
LY
C
URRENT
(A)
FIGURE 31. INPUT FILTERING
ISL2671286
+IN
–IN
VIN
CFILT
RFILT
IDC
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